Hello CarlosGarcia96,
unfortunatly (and I don't know why) my blog is offline for the moment.
In the first article of my blog (you can find an update version here : https://philippe-boudot.developpez.com/arduino-mkr-vidor4000/presentation/
I explained how the FPGA bitstream is uploaded in the FPGA.
For VHDL programmation, you should just rewrite the top level verilog file in VHDL, and add your own code
Philippe