Excuse me, but referring to the DUE main page assertion, about 3.3 volt pins : "They operate at 3.3 volts. Each pin can provide (source) a current of 3 mA or 15 mA, depending on the pin, or receive (sink) a current of 6 mA or 9 mA, depending on the pin."
I've not been able to find on the Net, informations about WHICH DUE pin can hold HOW MUCH ( 6 or 9 mA ) current. I think it's a very important information, if you want to connect even a single LED, or to design a voltage level shifter.
Can anybody help me?
I'll try to avoid opening another thread but, there are still some questions:
the values from above I think they are the maximum values that DUE can output or sink.
what are the minimum values, for example for inputs. What is the minimum current at 3.3V that due needs to have to consider a 1 (for digital ports) and which is the recommended (for example).
Not something many people need to consider, mostly we are interested in voltage on an input as it's hard to imaging a signal source that would be so weak as to not drive a FET gate as even RF in the air can do that.
Do you have a practical reason for wanting to know, or is it just an academic exercise?
what are the minimum values, for example for inputs. What is the minimum current at 3.3V that due needs to have to consider a 1 (for digital ports) and which is the recommended (for example).
EDIT: Unless I misunderstand what you're asking here, if you're trying to find out the minimum input current it takes for the input voltage levels to safely cross VIL and VIH, I would refer to the same datasheet page (1391) where: For Group 2(3) Pins, If no pull-up or pull-down is used, then look at the "Input Low Leakage Current" where its max value is 30nA and the "Input High Leakage Current" with max value of 18nA. For Group 1(2) Pins - not specified - same as above ???.
If we use ohm's law with 30nA and 3.3V we get 110M ohm. For high input resistance, we also need to consider that the input capacitance would limit the maximum bandwidth. For analog inputs, input capacitance is specified at 8 pf, but for digital inputs its TBA ... (probably around 8 pf) but this is yet another hole in the datasheet.
Those input leakage currents are worst case across the temperature range(*), at room temperature the input current
may well be measured in pA, not nA, Basically CMOS has infinite input resistance (to all practical purposes)
(its due to reverse biased pn-junctions in the protection diodes and output transistors - the input gate oxide
are 10^12 ohms or so and undetectable compared to this leakage)
Note that for lower voltage CMOS (1V1, that sort of supply voltage) gate oxide starts to exhibit leakage currents
due to quantum tunneling, but for a 3V3 chip this isn't an issue, inputs can be modelled as just a couple of pF.
I thanks everybody up, for the proper answers. I thought to make a simple list in excell , more readable than pag. 1391, to non -expert, like me, resuming current value per each pin, but I had no time to do it until now Thank you again!
