Vidor 4000 - FPGA programming/interaction

Hi CarlosGarcia96,

CarlosGarcia96:
When you mean download the bitstream .sof, it's to open the project in Quartus and run "compile design"?

Yes, that's right.

CarlosGarcia96:
If so, it says the stp2.stp file in output files is missing and I see no update in the previous MKRVIDOR4000_gdev_lite.sof that was already in the folder.

Thank you for your report, it is my mistake.

The stp2.stp file is a config file for the "Signal Tap Logic Analyzer". I debugged my design using it, and I forgot to disable it in the project setting before push my project to GitHub.

I updated the repository, so please pull the update.

Edit
You can manually disable the "Signal Tap Logic Analyzer" by the following steps:

  • Open MKRVIDOR4000_gdev_lite.qpf in the build directory by the Quartus.
  • Right-click the "MKRVIDOR4000_top" in the Project Navigator pane, and choose the "Settings..."
  • Select the "Signal Tap Logic Analyzer" from the "Category" list, and uncheck the "Enable Signal Tap Logic Analyzer".