TUCTUC77:
I can have it but the signals seems to be in opposite phase
dac_write (0xFFF & ~val) ; // copy inverted to DAC output FIFO
BTW, there is an interrupt after each and every conversion ( 1000 times per second). A more rational sampling method would be to fill a sampling buffer (e.g. 128 values), output this buffer thru a DAC while continuously sampling to fill another buffer with a PDC DMA thus dividing interrupts by a 128 scale.