[WORKFLOW RELEASE] Vidor sample projects are opensource!

Hi,

Thanks for the updated files, the Quartus patches seem to work fine now!

I am having problems running the example files however (starting with a slightly modified bare example that should set an output pin to 1 lighting up an LED). If I merely create an Arduino library (as is suggested in the github readme), the Arduino IDE complains that FPGA is defined twice (once in the VidorFPGA.cpp file in the VidorPeripherals library and once in my test library). I can comment out the offending lines in either of the libraries, but I am not certain how to figure out which app.ttf gets loaded in the end.

I have not yet managed to turn the output LED on through code written in Quartus. It seems to me that no matter what app.ttf I try to load, the example sketches from VidorPeripherals (setting outputs to on and off) seem to work. This indicates to me that I am always just loading the pre-compiled FPGA code, am I misunderstanding something?

I have also tried running the blinking example sketch written by Philippe which was posted here earlier and while Quartus indicates that everything compiles fine, the LED connected to port 6 never blinks. Is there a way for me to debug whether I have a problem with my FPGA? (The VidorPeripheral examples work!)

EDIT: Turns out I had screwed up something during my early debugging attempts, restoring the bootloader (according to the other thread) fixed my issue.

Hello, what differences does the VHDL code/commands I write for a Xilinx have, comparing to the VHDL I am going to write for the MKRVidor4000?

alex5678:
Hello, what differences does the VHDL code/commands I write for a Xilinx have, comparing to the VHDL I am going to write for the MKRVidor4000?

FPGA is synthesized with Quartus Prime. They plan to use premade images for several usecase. If I remember right there was plan to do some web integration for fpga build.

Hardcore users download VidorBitstream repository and create own fpga bit files with Quartus Prime Lite or full version. When using nios console you can use provided shell scripts to build libraries for arduino ide.

Top module is made with verilog.

Here is something info about Coding Conventions and bus interface.
https://www.arduino.cc/en/Tutorial/VidorHDL

Hello,

If I understood correctly, I use VHDL commands with a prefix to each to command in order to be accepted from the Arduino Vidor's FPGA, right?

Thank you...

It's just naming convention for interface signals.

You just use Verilog or VHDL with specific module interface that their upcoming web tool supports.

You can create FPGA image from scratch or use github templates for creating your own bitstream and library for arduino. For this you need Quartus Prime or Quartus Prime Lite.

Hello Dario,

Regarding your post above:

  1. fpga flash memory mapped is structured as follows: first 512k are used for fpga boot image, second 512k are used by application image (around 300k are used for fpga binary and the rest for nios application code). The remaining 1mb is going to be used for user applications.. we're actually developing a flash file system to store resources such as fonts, bitmaps, etc.

Is this ready and/or what is the ETA for release of the flash file system?

Also - is there a detailed memory map of the system? Would be great to see the absolute addresses of the system.

Thanks,
John

Hi John,
a memory map is not available simply because it depends on what you have instantiated in the FPGA.
the only firm thing is that we have reserved the first MB of flash for two FPGA images. since images are smaller than 512K we have set an arbitrary pointer in flash, after the flash images, to which the processor is jumping to execute code.

internally in the FPGA you can get a memory map of the peripherals connected to the processor by looking at the system.h file in the bsp directory generated by the toolchain in the build/software dir of the project

I have followed all instructions on how to build one of the provided projects, but I continuously receive an error when attempting to run "build_all.sh" from within NIOS II:

Error (12006): Node instace "u0" instantiates undefined entity "MKRVIDOR4000_peripherals_lite_sys". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP. File: C:/intelFPGA_lite/18.1/VidorBitstream-release/projects/MKRVIDOR4000_peripherals/rtl/MKRVIDOR4000_peripherals_top.v Line: 399

This happens for both MKRVIDOR4000_peripherals as well as MKRVIDOR4000_graphics. Bare does not do this (I assume because there are no peripheral IPs included).

Quartus Prime Lite 18.1 is installed, patches script applied, Go installed, running build_all.sh from within project folder...not sure what else to try?

Peripherals project have _lite.qsys files in repository.

It's first building qsys netlist that is used as component in top verilog where your building fail.

I think I had some discussion before and posted some buildscript fixed for lite version

Figured it out, thanks.

Had to open the projects/MKRVIDOR4000_peripherals_lite_sys project, open Settings, Files and click Add All (then remove non Lite version qsys file).

Re-ran build_all.sh and Arduino project now compiles successfully!

Hi,

what about video performance? As I read Cyclone 10 LP is pretty slow device. Spec sheet says 640 Mbps in LVDS mode while MIPI is up to 1Gbps pre lane.

Are HDMI max resolution and fps known?

Best regards, Sergei

Sorry for linking Xilinx appnote
https://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf

There you can find different display resolution vs needed bandwith in TMDS.

With 650 Mbps you can have XGA (1024x768@60fps 24b)

thank you, Limba. I am OK with Xilinx :slight_smile:

Hi.

Apparently, the port of Adafruit GFX for VidorBistream needs some adjustments.
The code for filling the primitives will mostly use writeVLine() function, while SDRAM would much prefer the horizontal lines.

VStrakh:
Hi.

Apparently, the port of Adafruit GFX for VidorBistream needs some adjustments.
The code for filling the primitives will mostly use writeVLine() function, while SDRAM would much prefer the horizontal lines.

Also that's pretty slow if you have lite version NIOS II e. Recommend to use HW acceleration for H lines and BMP copy

What's the rules on using 'update_fw.sh' script?

I always get error from 'quartus_cdb' and 'quartus_asm', telling that I should run 'quartus_map' first with the top-level entity. Is it about the paths to database?
When I explicitly enter the /build subdir in the project, those steps are performed ok when done manually.
But then the entire 'update_fw.sh' won't run from within /build subdir.
Adding 'build/' path in front of $PROJECT_NAME in 'update_fw.sh' seemingly achieves the desired effect.

I think you have to call build_all.sh in project folder. you have to add scripts folder to path env variable.

Limba:
I think you have to call build_all.sh in project folder. you have to add scripts folder to path env variable.

Well, the whole idea of 'update_fw.sh' is to update the data to be put in on-chip ram, without recompiling the entire fpga project.
Maybe it's not used by the devs at all, or wasn't adapted to the flow/environment that was published on github...

you have compiled project at least one time?

Yes, of course. There would be nothing to update if 'build_all.sh' run wasn't successfully completed at least once :slight_smile: