Philippe,
I appreciate the answer. We're all busy - no rush - just wanted to ask.
I believe all that is needed to make this work is just to control the JTAG pins at the proper time during code loading - I thought maybe someone had worked that out already - but I will take a look at that. I am assuming right now that is possible with the 'sketch' approach.
I have sketches that run code only on the SAM and NINA - loading the Cyclone 10 LP while controlling the necessary pins - probably JTAG and maybe a few more; will allow the code to be loaded.
I am not necessarily asking how to make the FPGA code "workflow" work with what you've done - I'd rather have
a sketch that's independent so to speak of the "workflow" that just interfaces via controlled pins; like how the JTAG pins will be controlled to make this work. I thought this had been worked out already.
Thanks,
John