Logic sniffer shield

I always have to check how that is spelt

Me too, I usually launch the program and look at the title bar :slight_smile:

you are going to fill up the chip in 1.6 mS

Yes, I did the maths also, that's not a very long time. OTOH using an external clock for SPI it's a huge amount of data.

can handle massive sample sizes because it uploads them via "bulk USB"

True, and many is the time I have a high-speed burst of data separated by a long period.

That CPLD board looks interesting. I was an early adopter of PLDs back on the 80s but have got well out of touch. In those days I had to spend a few days down in Sydney working on the Altera CAD system in their offices. Now you can do it at home for $20. Unbelievable.

I guess you could add run length encoding, but that would probably double the hardware needed. Maybe I should look at that CPLD board again.

I know it's been done before and as I just pointed out in almost exactly the same way, but it's such a fun project maybe it's worth doing anyway.


Rob