I have been looking at this diagram for several days and for some reason I feel like I'm missing something.
What confuses me is that it says "Data is outputted [sic} on the falling edge of SCK" but it looks like data is output on the RISING edge!
Based on this diagram, I think this is SPI Mode 3. Am I right?
(by the way, CS1 and CS2 are just chip select pins for each "chip". The device has two "chips" (display drivers) sharing a common SPI bus).
I also think it's SPI mode 3
Edit: Nevermind. I found my problem. I forgot to use a tilde for bit clearing!
I did this:
[font=monospace]Set bit: PORT != _BV(PIN); // right[/font]
[font=monospace]Clr bit: PORT &= _BV(PIN); // wrong![/font]
should have been
[font=monospace]Clr bit: PORT &= ~_BV(PIN); // wrong![/font]