Arduino Forum

Products => MKR Boards => MKRVIDOR4000 => Topic started by: facchinm on Nov 24, 2018, 03:45 pm

Title: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: facchinm on Nov 24, 2018, 03:45 pm
Hi everyone!

We are finally announcing the availability of both source code and build tools to kickstart your next project with MKRVidor4000!

All the code is available at https://github.com/vidor-libraries/VidorBitstream (https://github.com/vidor-libraries/VidorBitstream) ready to be forked, compiled, modified and contributed back.

The projects we previously released as precompiled libraries (VidorGraphics and VidorPeripherals) have been adapted to a new, more flexible architecture, which allows to dynamically discovery which IPs are instantiated in the FPGA and, in case they need to control hardware pins, to require them very easily.

Moreover, we also release an experimental USB Blaster (https://github.com/vidor-libraries/USBBlaster) "emulator" that can run on the SAMD21 and provide a full fledged JTAG programmer directly connected to the Cyclone10 FPGA. Unfortunately we could only release it in precompiled format due to licensing issues, so you'll need SAMD core 1.6.25 (already available via Board Manager) to compile and link the library.

So, what are you waiting? Let's start hacking  8) !
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: ergoen on Nov 27, 2018, 07:06 am
Looking forward to trying this and learning some fpga programming! I would like to give a head-up about a problem with the Quartus patch however. On my Windows installation (latest 18.1) Quartus comes with source files with both CRLF and LF line endings. This causes the patch to fail with multiple errors like "Hunk #1 FAILED at 34 (different line endings).". The trivial fix of changing the path command to use the --binary flag also fails since some of the target files are CRLF and some are LF.

One suggestion would be to split up the patch files into two parts, one for each line ending. I'm not sure if this is the best (most pragmatic?) approach though.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: DarioPennisi on Nov 29, 2018, 07:49 am
Hi,
Patches are for 18.0. I had a look at your issue and have a fix for the crlf issue but there's a change that prevents a file to be updated so on 18.1 it's going to fail anyway. We're looking into it and will update soon, maybe even today
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: DarioPennisi on Nov 29, 2018, 05:45 pm
hi,
an update has been pushed to git. please update and let us know if this fixes compilation. this should fix both CRLF issues and 18.1 compatibility. note that when patching you will still receive an error on a hunk but that is ok as there is a difference between the 18.0 and 18.1 IP blocks and the hunk that does not apply is not required anymore for 18.1
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: sadr0b0t on Dec 09, 2018, 09:50 pm
Hello, thank's for posting this. Can you please clarify some points?

1. I can see major part of this project is a kind of quartus ip optimizations and build system extensions. But can I still just take default vanilla Quartus lite with no patches, build some simple Verilog project with no or minimal deps to external ip (for example, this one taken as a template https://github.com/vidor-libraries/VidorFPGA/tree/master/projects/MKRVIDOR4000_template) to ttf file, convert ttf, produced by Quartus, with createCompositeBinary utility and then incorporate converted ttf to Arduino cpp library. Would some basic staff work in this way or I will still miss something and will have to patch Quartus and use suggested build system anyway?

2. About createCompositeBinary utility readme says:

https://github.com/vidor-libraries/VidorBitstream/tree/release/TOOLS/makeCompositeBinary
Quote
Bitstreams produced by Quartus (in ttf format) are not suitable to be directly burned on the flash since their nibble encoding is reverse.
How come Altera (Intel) chip can't be burned with firmware produced by Altera's (Intel's) software? Where can I read about this?

3. I am looking at the way ttf file is incorporated to Arduino library and see it is loaded to bitstream array in VidorFPGA class like this:

Code: [Select]

__attribute__ ((used, section(".fpga_bitstream_signature")))
const unsigned char signatures[4096] = {
 #include "signature.h"
};
__attribute__ ((used, section(".fpga_bitstream")))
const unsigned char bitstream[] = {
 #include "app.ttf"
};


bitstream array constant is not used anywhere else in the code and __attribute__ instruction says its content should be placed to special ".fpga_bitstream" section inside Arduino compiled firmware file. So I can assume, that ".fpga_bitstream" section inside Vidor SAM chip is somehow connected to FPGA's firmware memory at hardware level (or loaded from SAM to FPGA either by SAM's or by FPGA's bootloader code at the start). So what is the actual way of ttf contents inside ".fpga_bitstream" section (when ttf is incorporated to Arduino library) coming to FPGA?

thank's
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: DarioPennisi on Dec 09, 2018, 10:46 pm
Hi,
Interesting questions. Let me try to answer them in a clear way...
1a) quartus patches are required only if your project uses qspi or serial port as these were modified by us.
1b) the template_bare project is really empty and just contains pinout and a pill. Template_mbox contains a qsys system where the mailbox between Sam and fpga is instantiated. There you can add in qsys your IP blocks and control them using the infrastructure we created (see mailbox and RPC docs under each IP for for reference).
2) the ttf produced by quartus has bits in bytes arrange in the opposite way the FPGA requires them as serialized by the flash. Actually quartus could produce a end file with proper order but it requires post processing as it's not generated at compile time and needs to be converted to text in order to be compiled with the arm application. To summarize, no, quartus does not produce a text file which can be directly compiled and loaded in flash and in any case usually it produces binary files loaded directly by quartus via JTAG.
3) in order create a single binary image we are loading fpga code in a section loaded after the end of Sam d21 flash. This is a trick that allows bossac and bootloader to figure out that the binary file is to be loaded somewhere else, by sending that data to JTAG instead of Sam d21 flash. The idea is that when data exceeding d21 memory is received, that is sent to fpga that writes it to locations of the fpga application space (located after the fpga boot image).
4) fpga flash memory mapped is structured as follows: first 512k are used for fpga boot image, second 512k are used by application image (around 300k are used for fpga binary and the rest for nios application code). The remaining 1mb is going to be used for user applications.. we're actually developing a flash file system to store resources such as fonts, bitmaps, etc.

Hope this clarifies things a bit
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: ergoen on Jan 05, 2019, 02:25 pm
Hi,

Thanks for the updated files, the Quartus patches seem to work fine now!

I am having problems running the example files however (starting with a slightly modified bare example that should set an output pin to 1 lighting up an LED). If I merely create an Arduino library (as is suggested in the github readme), the Arduino IDE complains that FPGA is defined twice (once in the VidorFPGA.cpp file in the VidorPeripherals library and once in my test library). I can comment out the offending lines in either of the libraries, but I am not certain how to figure out which app.ttf gets loaded in the end.

I have not yet managed to turn the output LED on through code written in Quartus. It seems to me that no matter what app.ttf I try to load, the example sketches from VidorPeripherals (setting outputs to on and off) seem to work. This indicates to me that I am always just loading the pre-compiled FPGA code, am I misunderstanding something?

I have also tried running the blinking example sketch written by Philippe which was posted here earlier and while Quartus indicates that everything compiles fine, the LED connected to port 6 never blinks. Is there a way for me to debug whether I have a problem with my FPGA? (The VidorPeripheral examples work!)

EDIT: Turns out I had screwed up something during my early debugging attempts, restoring the bootloader (according to the other thread) fixed my issue.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: alex5678 on Jan 11, 2019, 12:51 pm
Hello, what differences does the VHDL code/commands I write for a Xilinx have, comparing to the VHDL I am going to write for the MKRVidor4000?
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on Jan 12, 2019, 12:05 am
Hello, what differences does the VHDL code/commands I write for a Xilinx have, comparing to the VHDL I am going to write for the MKRVidor4000?
FPGA is synthesized with Quartus Prime. They plan to use premade images for several usecase. If I remember right there was plan to do some web integration for fpga build.

Hardcore users download VidorBitstream repository and create own fpga bit files with Quartus Prime Lite or full version. When using nios console you can use provided shell scripts to build libraries for arduino ide.

Top module is made with verilog.

Here is something info about Coding Conventions and bus interface.
https://www.arduino.cc/en/Tutorial/VidorHDL (https://www.arduino.cc/en/Tutorial/VidorHDL)
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: alex5678 on Jan 13, 2019, 02:38 pm
Hello,

If I understood correctly, I use VHDL commands with a prefix to each to command in order to be accepted from the Arduino Vidor's FPGA, right?

Thank you...
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on Jan 13, 2019, 06:07 pm
It's just naming convention for interface signals.

You just use Verilog or VHDL with specific module interface that their upcoming web tool supports.

You can create FPGA image from scratch or use github templates for creating your own bitstream and library for arduino. For this you need Quartus Prime or Quartus Prime Lite.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: jwestmoreland on Jan 26, 2019, 10:12 am
Hello Dario,

Regarding your post above:

4) fpga flash memory mapped is structured as follows: first 512k are used for fpga boot image, second 512k are used by application image (around 300k are used for fpga binary and the rest for nios application code). The remaining 1mb is going to be used for user applications.. we're actually developing a flash file system to store resources such as fonts, bitmaps, etc.

Is this ready and/or what is the ETA for release of the flash file system?

Also - is there a detailed memory map of the system?  Would be great to see the absolute addresses of the system.

Thanks,
John
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: DarioPennisi on Jan 31, 2019, 04:16 pm
Hi John,
a memory map is not available simply because it depends on what you have instantiated in the FPGA.
the only firm thing is that we have reserved the first MB of flash for two FPGA images. since images are smaller than 512K we have set an arbitrary pointer in flash, after the flash images, to which the processor is jumping to execute code.

internally in the FPGA you can get a memory map of the peripherals connected to the processor by looking at the system.h file in the bsp directory generated by the toolchain in the build/software dir of the project
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: mbyington on Mar 25, 2019, 07:39 pm
I have followed all instructions on how to build one of the provided projects, but I continuously receive an error when attempting to run "build_all.sh" from within NIOS II:

Error (12006): Node instace "u0" instantiates undefined entity "MKRVIDOR4000_peripherals_lite_sys". Ensure that required library paths are specified correctly, define the specified entity, or change the instantiation. If this entity represents Intel FPGA or third-party IP, generate the synthesis files for the IP. File: C:/intelFPGA_lite/18.1/VidorBitstream-release/projects/MKRVIDOR4000_peripherals/rtl/MKRVIDOR4000_peripherals_top.v Line: 399

This happens for both MKRVIDOR4000_peripherals as well as MKRVIDOR4000_graphics. Bare does not do this (I assume because there are no peripheral IPs included).

Quartus Prime Lite 18.1 is installed, patches script applied, Go installed, running build_all.sh from within project folder...not sure what else to try?
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on Mar 27, 2019, 06:16 pm
Peripherals project have _lite.qsys files in repository.

It's first building qsys netlist that is used as component in top verilog where your building fail.

I think I had some discussion before and posted some buildscript fixed for lite version
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: mbyington on Mar 27, 2019, 07:45 pm
Figured it out, thanks.

Had to open the projects/MKRVIDOR4000_peripherals_lite_sys project, open Settings, Files and click Add All (then remove non Lite version qsys file).

Re-ran build_all.sh and Arduino project now compiles successfully!
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: SergeiB on Mar 28, 2019, 04:08 pm
Hi,

what about video performance? As I read Cyclone 10 LP is pretty slow device. Spec sheet says 640 Mbps in LVDS mode while MIPI is up to 1Gbps pre lane.

Are HDMI max resolution and fps known?

Best regards, Sergei
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on Mar 28, 2019, 05:35 pm
Sorry for linking Xilinx appnote
https://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf (https://www.xilinx.com/support/documentation/application_notes/xapp495_S6TMDS_Video_Interface.pdf)

There you can find different display resolution vs needed bandwith in TMDS.

With 650 Mbps you can have XGA (1024x768@60fps 24b)
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: SergeiB on Mar 28, 2019, 06:50 pm
thank you, Limba. I am OK with Xilinx :)
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: VStrakh on Apr 09, 2019, 10:10 pm
Hi.

Apparently, the port of Adafruit GFX for VidorBistream needs some adjustments.
The code for filling the primitives will mostly use writeVLine() function, while  SDRAM would much prefer the horizontal lines.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on Apr 10, 2019, 10:20 am
Hi.

Apparently, the port of Adafruit GFX for VidorBistream needs some adjustments.
The code for filling the primitives will mostly use writeVLine() function, while  SDRAM would much prefer the horizontal lines.
Also that's pretty slow if you have lite version NIOS II e. Recommend to use HW acceleration for H lines and BMP copy
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: VStrakh on Apr 10, 2019, 09:07 pm
What's the rules on using 'update_fw.sh' script?

I always get error from 'quartus_cdb' and 'quartus_asm', telling that I should run 'quartus_map' first with the top-level entity. Is it about the paths to database?
When I explicitly enter the /build subdir in the project, those steps are performed ok when done manually.
But then the entire 'update_fw.sh' won't run from within /build subdir.
Adding 'build/' path in front of $PROJECT_NAME in 'update_fw.sh' seemingly achieves the desired effect.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on Apr 10, 2019, 10:20 pm
I think you have to call build_all.sh in project folder. you have to add scripts folder to path env variable.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: VStrakh on Apr 10, 2019, 11:49 pm
I think you have to call build_all.sh in project folder. you have to add scripts folder to path env variable.
Well, the whole idea of 'update_fw.sh' is to update the data to be put in on-chip ram, without recompiling the entire fpga project.
Maybe it's not used by the devs at all, or wasn't adapted to the flow/environment that was published on github...
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on Apr 11, 2019, 12:26 am
you have compiled project at least one time?
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: VStrakh on Apr 11, 2019, 07:26 am
Yes, of course. There would be nothing to update if 'build_all.sh' run wasn't successfully completed at least once :)
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: arduardu999 on May 07, 2019, 11:53 am
Hello I am arduino/VHDL user, and I wanted more powerful camera for my project with parallel data connection, it can be used as bridge between my fpga and camera with standard 1080p, 480p in highspeed .

for this purpose i need to connect ov4689 camerachip with MIPI interface, is it possible to use this and how about source code in vhdl ? source code in vhdl which is MIPI to parallel data and HDMI output (to check whther it works or not )

can you provide all source codes free ?
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Limba on May 07, 2019, 09:50 pm
Were you planning to use mipi_rx_st ip in another device than vidor?
Maybe study that that ip how mipi receiver is done and create your own ip. IP is done with System Verilog.

If you have C/C++/C# experience then System Verilog syntax is not that hard.

MIPI_RX_ST
Input: MIPI RX and MIPI CLK.
Ouput: Avalon steam master

Edit:
It also seems to do Bayer to RGB filtering. There's more info in wikipedia and it's commented in code.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: Kergadon on Jun 12, 2019, 08:14 pm
Not sure if this is the place to do it but I can't seem to build the MKRVIDOR4000_template_mbox project

First of all the output looks completely different from when I try to compile MKRVIDOR4000_template_bare (which seems to work)

As far as I can figure out the issue seems to be this bit

2019.06.12.11:59:41 Info: Adding qspi [arduino_generic_quad_spi_controller2 18.1]
2019.06.12.11:59:41 Warning: qspi: Component type <b>arduino_generic_quad_spi_controller2</b> is not in the library


I also included the whole output in the case that is needed.

Code: [Select]

$ I:/Downloads/VidorBitstream/TOOLS/scripts/build_all.sh
2019.06.12.12:10:48 Info: Saving generation log to I:/Downloads/VidorBitstream/projects/MKRVIDOR4000_template_mbox/build/MKRVIDOR4000_template_mbox_lite_sys/MKRVIDOR4000_template_mbox_lite_sys_generation.rpt
2019.06.12.12:10:48 Info: Starting: <b>Create HDL design files for synthesis</b>
2019.06.12.12:10:48 Info: qsys-generate I:\Downloads\VidorBitstream\projects\MKRVIDOR4000_template_mbox\build\MKRVIDOR4000_template_mbox_lite_sys.qsys --synthesis=VERILOG --output-directory=I:\Downloads\VidorBitstream\projects\MKRVIDOR4000_template_mbox\build\MKRVIDOR4000_template_mbox_lite_sys\synthesis --family="Cyclone 10 LP" --part=10CL016YU256C8G
2019.06.12.12:10:48 Info: Loading build/MKRVIDOR4000_template_mbox_lite_sys.qsys
2019.06.12.12:10:48 Info: Reading input file
2019.06.12.12:10:48 Info: Adding JTAG_BRIDGE_0 [JTAG_BRIDGE 1.0]
2019.06.12.12:10:48 Info: Parameterizing module JTAG_BRIDGE_0
2019.06.12.12:10:48 Info: Adding clk [clock_source 18.1]
2019.06.12.12:10:48 Info: Parameterizing module clk
2019.06.12.12:10:48 Info: Adding flash_clk [clock_source 18.1]
2019.06.12.12:10:48 Info: Parameterizing module flash_clk
2019.06.12.12:10:48 Info: Adding flash_spi [tiny_spi 1.0]
2019.06.12.12:10:48 Info: Parameterizing module flash_spi
2019.06.12.12:10:48 Info: Adding mb [MAILBOX 1.0]
2019.06.12.12:10:48 Info: Parameterizing module mb
2019.06.12.12:10:48 Info: Adding nina_spi [tiny_spi 1.0]
2019.06.12.12:10:48 Info: Parameterizing module nina_spi
2019.06.12.12:10:48 Info: Adding nios2_gen2_0 [altera_nios2_gen2 18.1]
2019.06.12.12:10:48 Info: Parameterizing module nios2_gen2_0
2019.06.12.12:10:48 Info: Adding onchip_memory2_0 [altera_avalon_onchip_memory2 18.1]
2019.06.12.12:10:48 Info: Parameterizing module onchip_memory2_0
2019.06.12.12:10:48 Info: Adding pex_pio [PIO 1.0]
2019.06.12.12:10:48 Info: Parameterizing module pex_pio
2019.06.12.12:10:48 Info: Adding qspi [arduino_generic_quad_spi_controller2 18.1]
2019.06.12.12:10:48 Warning: qspi: Component type <b>arduino_generic_quad_spi_controller2</b> is not in the library
2019.06.12.12:10:48 Info: Parameterizing module qspi
2019.06.12.12:10:48 Info: Adding sam_pio [PIO 1.0]
2019.06.12.12:10:48 Info: Parameterizing module sam_pio
2019.06.12.12:10:48 Info: Adding sam_pwm [PWM 1.0]
2019.06.12.12:10:48 Info: Parameterizing module sam_pwm
2019.06.12.12:10:48 Info: Adding sdram [altera_avalon_new_sdram_controller 18.1]
2019.06.12.12:10:48 Info: Parameterizing module sdram
2019.06.12.12:10:48 Info: Adding sysid_qsys_0 [altera_avalon_sysid_qsys 18.1]
2019.06.12.12:10:48 Info: Parameterizing module sysid_qsys_0
2019.06.12.12:10:48 Info: Adding timer_0 [altera_avalon_timer 18.1]
2019.06.12.12:10:48 Info: Parameterizing module timer_0
2019.06.12.12:10:48 Info: Adding wm_pio [PIO 1.0]
2019.06.12.12:10:48 Info: Parameterizing module wm_pio
2019.06.12.12:10:48 Info: Building connections
2019.06.12.12:10:48 Info: Parameterizing connections
2019.06.12.12:10:48 Info: Validating
2019.06.12.12:10:49 Info: Done reading input file
2019.06.12.12:10:51 Error: MKRVIDOR4000_template_mbox_lite_sys.qspi: Component <b>arduino_generic_quad_spi_controller2 18.1</b> not found or could not be instantiated
2019.06.12.12:10:51 Info: MKRVIDOR4000_template_mbox_lite_sys.sdram: SDRAM Controller will only be supported in Quartus Prime Standard Edition in the future release.
2019.06.12.12:10:51 Info: MKRVIDOR4000_template_mbox_lite_sys.sysid_qsys_0: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
2019.06.12.12:10:51 Info: MKRVIDOR4000_template_mbox_lite_sys.sysid_qsys_0: Time stamp will be automatically updated when this component is generated.
2019.06.12.12:10:51 Warning: MKRVIDOR4000_template_mbox_lite_sys.JTAG_BRIDGE_0: Interrupt sender <b>JTAG_BRIDGE_0.irq</b> is not connected to an interrupt receiver
2019.06.12.12:10:51 Warning: MKRVIDOR4000_template_mbox_lite_sys.flash_spi: Interrupt sender <b>flash_spi.irq</b> is not connected to an interrupt receiver
2019.06.12.12:10:51 Warning: MKRVIDOR4000_template_mbox_lite_sys.nina_spi: Interrupt sender <b>nina_spi.irq</b> is not connected to an interrupt receiver
2019.06.12.12:10:51 Warning: MKRVIDOR4000_template_mbox_lite_sys.JTAG_BRIDGE_0: <b>JTAG_BRIDGE_0.event</b> must be connected to an Avalon-MM master
2019.06.12.12:10:51 Error: MKRVIDOR4000_template_mbox_lite_sys.qspi.avl_mem: Data width must be of power of two and between 8 and 4096
2019.06.12.12:10:51 Info: MKRVIDOR4000_template_mbox_lite_sys: Generating <b>MKRVIDOR4000_template_mbox_lite_sys</b> "<b>MKRVIDOR4000_template_mbox_lite_sys</b>" for QUARTUS_SYNTH
2019.06.12.12:10:53 Info: Interconnect is inserted between master JTAG_BRIDGE_0.avalon_master and slave mb.mst because the master has address signal 32 bit wide, but the slave is 9 bit wide.
2019.06.12.12:10:53 Info: Interconnect is inserted between master JTAG_BRIDGE_0.avalon_master and slave mb.mst because the master has waitrequest signal 1 bit wide, but the slave is 0 bit wide.
2019.06.12.12:10:53 Info: Interconnect is inserted between master JTAG_BRIDGE_0.avalon_master and slave mb.mst because the master has readdatavalid signal 1 bit wide, but the slave is 0 bit wide.
2019.06.12.12:10:55 Error: null


Thanks in advanced for any help or advice.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: VStrakh on Jun 13, 2019, 10:15 am
2019.06.12.11:59:41 Info: Adding qspi [arduino_generic_quad_spi_controller2 18.1]
2019.06.12.11:59:41 Warning: qspi: Component type <b>arduino_generic_quad_spi_controller2</b> is not in the library
Did you apply patches to Quartus? You need to do it once.

Run the NIOS II Command shell, move to the TOOLS/scripts directory of the VidorBistream repository, and launch the 'apply_quartus_patches.sh'
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: jomoengineer on Jun 22, 2019, 07:45 pm
I ran into the build error as well and found I had to run through the following on Windows 10 64-bit to get a successful build:
NOTE: This was parsed from the vidor-libraries/VidorBitstream github repo under:
"Things to know before getting started"

1. Open the  NIOS II Command shell and set the PATH variable:
    $ PATH=$PATH:/cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/TOOLS/scripts
    NOTE: This was valid for my config.

2. Then change directories to the VidorBitstream directory.
    NOTE: I did this from one directory up instead.
 
    $ cd /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/

    or

    $ cd /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga

3.  Set the permissions to the files under VidorBitstream

    $ chmod -R a+rw *

4. Then under the TOOLS/scripts directory, run the patch script
   $ cd /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/TOOLS/scripts

   $ apply_quartus_patches.sh

5. Download and install the GO Programming language and build makeCompositeBinary.
   $ cd ../makeCompositeBinary
   
   $ go build -o makeCompositeBinary make_composite_binary.go

6. Build an example:
   $ cd /cygdrive/h/Development/Arduino_config/MKR_Vidor_4000/fpga/VidorBitstream/projects/MKRVIDOR4000_graphics

   $ build_all.sh

This resulted in the following for me:
Code: [Select]
Info: Quartus Prime Shell was successful. 0 errors, 352 warnings
    Info: Peak virtual memory: 4626 megabytes
    Info: Processing ended: Sat Jun 22 02:28:30 2019
    Info: Elapsed time: 00:06:33
    Info: Total CPU time (on all processors): 00:00:05
create ram + flash app.ttf
Jun 22, 2019 2:28:30 AM - (INFO) elf2flash: args = --input=build/software/MKRVIDOR4000_graphics/MKRVIDOR4000_graphics_lite.elf --output=build/output_files/MKRVIDOR4000_graphics_lite.flash --base=0x008E0000 --end=0x008FFFFF --verbose --save
Jun 22, 2019 2:28:30 AM - (FINE) elf2flash: Starting
Jun 22, 2019 2:28:30 AM - (FINE) elf2flash: Done
projects
ip
cp: omitting directory './ip/GFX/arduino/Vidor_GFX/examples'
cp: omitting directory './ip/QUAD_ENCODER/arduino/VidorEncoder/examples'
cp: omitting directory './ip/NEOPIXEL/arduino/VidorNeopixel/examples'
cp: omitting directory './ip/MIPI_RX_ST/arduino/VidorCamera/examples'




I hope this is on topic.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: jomoengineer on Jun 26, 2019, 04:26 pm
After perfoming the VidorBistream build process and replacing the existing VidorGraphics Arduino IDE libraries folder with that built from VidorBitstream, ex;VidorBitstream\distrib\MKRVIDOR4000_graphics, as Martino explained to me has rendered my Vidor 4000 Graphics as non functional. I put the original library files back in place but still no luck; none of the VidorGraphics examples or code I had previously created and which were working are working now.  All I get on the HDMI output is a white screen with the Arduino log in the middle but not the one from the DrawLogo example.
Title: Re: [WORKFLOW RELEASE] Vidor sample projects are opensource!
Post by: jomoengineer on Jun 26, 2019, 04:35 pm
Okay, so I downloaded, built and loaded  VidorBoot from the vidor-libraries GitHub repro and all is right again with the Vidor 4000.