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Topic: I2S Slave mode (Read 179 times) previous topic - next topic


Hello there,
How does slave mode work with I2S?

1. Does this work as following: an external interrupt decides the sample frequency?
2. How do you swich between L/R channel?
3. Which pin does it read from??

void setup() {
  pinMode(A1, INPUT_PULLUP);
  void interrupt();
  attachInterrupt(digitalPinToInterrupt(A1), interrupt, RISING);

  I2S.begin(I2S_PHILIPS_MODE, 24);

void loop() {
  //Other things happening here

void interrupt() {
  int sample = I2S.read();


Apr 18, 2019, 10:04 am Last Edit: Apr 18, 2019, 10:12 am by Grumpy_Mike
Not sure I understand the concept of I2S slave mode, the bus is bi-directional.

1. Does this work as following: an external interrupt decides the sample frequency?
No. The I2S device will have an input pin for digitising an audio input. The sample rate is determined by a message you send it

How do you swich between L/R channel?
You send a message to the I2S device saying stereo or mono. If it is stereo both channels are encoded in the packet you get back and if you only want one then you parse it out.

Which pin does it read from?
See the data sheet on your I2S device. Note a lot of devices are receive only so make sure you use one that can also send a signal.
This is a breakout board that will do inputs


Apr 20, 2019, 12:28 am Last Edit: Apr 20, 2019, 12:30 am by MarkT
All slave mode means is some other device is generating the clocks.  Normally the host microcontroller or
DSP is the only master.

Most devices just need the right clocks and they simply work straight off at the relevant sample rate
and resolution.  SPI or some control pins may allow setting mono/stereo or LJ/RJ/I2S bit justification.

The default is normally stereo, and one of the clocks (LRCLK) determines which sample is left and which is right
(they alternate in time).  Consult a few I2S device datasheets.

Most devices take all three clocks (MCLK, BCLK, LRCLK), some can generate MCLK using an internal PLL
(although this means inferior analog performance due to the jitter).  The clocks must be frequency locked,
and BCLK and LRCLK must have the correct phase relationship.

I2S is not designed for software or even interrupt use, its a hardware to hardware synchonous serial path.

The clocks are normally derived from 12.288MHz or 6.144MHz crystals, and they must be quartz accurate, ie stable and low jitter.
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