PWM has a fixed frequency and a resolution limited by the clock cycles per PWM cycle.
With Sigma-delta the input value is summed to an error register and the output subtracts
from that register - in effect there is a feedback loop trying to keep the error within bounds,
and the input resolution is decoupled from the output resolution.
You can use single-bit output, in which case the proportion of ones in the output (averaged
over time) is proportional to the input value (which can be 16 or more bits if you want). The
frequency of the output is not constant and usually the signal needs converting to analog
with a very tight-spec charge-summing stage (the precise timing of the clock edges is all-important
in getting good linearity).
But you can also use PWM as the output, say 8-bit PWM out, 16 bits in, and the error value
has its top 8 bits pushed out to the PWM every PWM period - the lower order bits are still
accounted for and provide high resolution at low bandwidth.
In general sigma-delta trades bandwidth for accuracy (clock has to run a lot faster than the
sample rate).
Real converters use more tricks and are more complex, but the basic idea is to maintain
an error value and use negative feedback to keep the accumulated error small.