I couldn't figure out an easy way to do that without a current probe, I can try adding a small series
Hi guys I suspect that the need for a gate resistor, might be a "folk memory", passed down by 'generations' of old farts like me, who have never had any need or reason to doubt the accepted wisdom.Fof
Hi guysThoroughly enjoyed this very informative thread.Here are a couple of thoughts I've had. In my professional career, I spent most of my time in development labs, working directly and in parallel with lots of very clever EEs. They, invariably, like me, tended to include a small gate resistor. This thread has got me thinking as to where the gate resistor requirement came from.Very many of you will never have come across the situation where it was obligatory to attach heat shunts to the legs of transistors, before applying a soldering iron. Yes, when transistors first started to appear in commercial devices, this is what we had to do. Ever hear of the expression "the fastest fuse on three legs"? This is what transistors were commonly called, as they would die, just by looking at them the wrong way. We used to joke that they were only there to protect the main fuse.In these sort of scenarios, if I was a design engineer, I would use each and every form of insurance I could incorporate. Don't forget that the development of transistors took quite a few years before one could (almost) guarantee many of the stated characteristics and parameters required for the design.As FETs have always been the 'delicate' flower compared to BJT, due to potential for static damage, I suspect that the need for a gate resistor, might be a "folk memory", passed down by 'generations' of old farts like me, who have never had any need or reason to doubt the accepted wisdom.Thanks for a great, educational read.Fof
The cascode configuration works with BJT, JFETs, MOSFETs, and a mixture of them. It also means you can stack transistors to get a higher voltage than any individual rating.
Hi again,The original gate resistor requirement came from the oscillation due to there being some inductance in every mosfet source circuit.
Yes this was my understanding as well MrAl. I've certainly seen this oscillation effect occur, and it can quite drastically increase the switching losses. Reducing the source inductance (the length and layout of wiring from source to common ground point with gate drive) and/or increasing the gate series resistance is the cure.Regarding the other issue of transient pin power dissipation and the danger of overloading the pin without the resistor, I very much doubt that this is an issue with small mosfets as per the OP's example (2n7000).Of course it depends on what voltage you're switching, but the typical value of total gate charge for that mosfet is only around 1nC. So we have about 1nC * 5V = 5nJ of energy loss per switching cycle. Even at 100 kHz that only amounts to 0.0005 Watts of additional dissipation in the micro controller.Regarding the instantaneous power dissipation that may occur while switching, consider the pin output characteristics (taken from 328P datasheet) below. Note that the output resistance is about 25 ohms (20mA at 0.5V drop). Also note the slight curvature of the characteristics, showing increasing resistance with increased voltage drop as is typical for a mos output.So we could estimate that the maximum instantaneous power dissipation would be somewhat less than 100mA * 2.5 V = 0.25 Watts, albeit very briefly.Personally I would be very surprised if the power dissipation (instantaneous or otherwise) would be an issue. Even for larger mosfets I suspect that the need for an external driver (to achieve snappier switching and reduce switching losses in the mosfet) would arise well before damaging power losses occurred in the MPU pins.Having said that however. Not everyone has an oscilloscope to detect unwanted oscillations, or the ability to layout the gate drive to avoid it, so guidelines like adding the series gate resistance really aren't a bad idea in any case.
MOSFET designers do a lot to reduce the Miller capacitance in devices, its not that important at low voltages.The plateau is where the channel is formed, basically - the charge in the gate mirrors the charges formingthe gate. Most of the channel area is protected from the drain voltage since the substrate is electricallyconnected to the source.There is, of course, still some drain-gate capacitance, but the total charge on the gate is much largerthan the charge on this capacitance in a good device.I did some experiments switching 3A with a drain voltage of 0.5V, 9V and about 25V on an STP3020Llogic-level StripFET, and the fall in drain voltage (blue) happens basically before the bulk of the gatecharge. The gate drive is an Arduino pin (so about 30 or 40 ohm source impedance)Note the horizontal scale is 25ns/div, vertical is 1V/div for yellow (gate voltage), 5V/div for drain(blue).The time taken to charge the plateau is extended for larger drain voltages, which suggests some sortof delayed Miller effect, but note the plateau is present even at a 0.5V drain voltage, when the Millereffect is for all purposes absent.Note also the sudden onset of drain voltage falling at the moment the plateau starts - clearly thisis when a channel first forms (the inversion layer)[ Note that due to the bench power supply and long leads I didn't get meaningful switch-off waveforms, and thinking about it I suspect the change of charge in the drift region is probably responsible for the delayed second part of the plateau - that change is proportional to the drain delta-V... ]
As FETs have always been the 'delicate' flower compared to BJT, due to potential for static damage,
We used to joke that they were only there to protect the main fuse.