Hi,The usual argument centers on the use of a series gate resistor in order to reduce oscillations that cause the MOSFET to turn on and off repeatedly while the source inductance path combined with various capacitances oscillates as an RLC circuit would when presented with a step input drive signal. It oscillates for a time, then depending on the R value, starts to damp out toward steady state Once steady state is reached, the circuit
Yes.I am currently using a borrowed 2 GHz scope to do some tests.Plenty of ringing on a breadboard circuit.Not so on a soldered board with some thought to layout.Many here are capable of building aerospace and medical equipment and doing the sums themselves.Most i suspect are beginners who really only need advice on how to prevent destroying their (fairly expensive toys).A 3 cent resistor would appear to be a reasonable solution. Bit of a generalisation though.Semantics may be the problem. Stating that a gate resistor is required can fly in the face of a professional engineer but is possibly good advice for a beginner.
Do we have any consensus on what the equivalent series resistance of say the Uno chip pin has when going high?
Hi,That's great to hear, and i was also thinking we could estimate the chip pin wave as a ramp followed by a plateau followed by another ramp most likely.
Reading the thread i think the ESR is between 20 to 40 ohms.Not had the chance to set up a suitable experiment though, BILLO i think tried it.I have limited time with equipment , any suitable suggestions for experimentation ?Even if i understood that proprerly, it will probably take me a month to learn how to drive the machine.
For the Arduino chip or any other uC chip, the signal at the gate will look like an exponential followed by a plateau, followed by another exponential.
International Rectifier gave a really good talk on this in one of their data books on HexFets, but i am not sure where that document is online anymore, or if it is online anymore. I suspect it can be found on their website irf.com.Do we have any consensus on what the equivalent series resistance of say the Uno chip pin has when going high?
I know I wasn't going to post in this thread anymore, but what you mentioned is worth a comment.The two "exponentials" that you see have different causes.The first one is due to the Miller effect combined with the inherent gate capacitance of the MOSFET. The "plateau" you see is when the drain is pulled as low as it's going to go, then finally the second exponential is the gate capacitance alone charging to Vgs equilibrium.I don't think most people really know what the Miller effect is. Anywhere you look it up online, there are all kinds of formulas and hokey-pokey, but no clear explanation of the actual mechanism.Imagine any 3 terminal (triode) device such as a BJT, a MOSFET and even a vacuum tube triode.There is inherent capacitance that exists between each terminal and every other terminal, but the one that causes the Miller effect is the drain to gate capacitance (or collector to base, or plate to grid).Imagine a MOSFET with the drain is being used to switch an LED on through the appropriate resistor.Initially, the drain is at Vdd (minus the drop across the LED) and the gate is at 0.Therefore, the inherent capacitor between the drain and gate is charged to Vdd - V-LED.Now, begin to raise the gate voltage. As the MOSFET begins to turn on, the drain begins to lower, beginning to turn on the LED and also lowering the drain side of the inherent capacitor.Of course, the gate side of the capacitor will also start to lower, which is FIGHTING the thing trying to drive the gate high.The gate ends up looking like a LARGER capacitor which takes a lot of current to charge.Once the MOSFET is saturated (that is, Vgs is at it's minimum), the "capacitance amplifying effect" stops and you get the plateau. Finally, you get another, less "severe" exponential as the gate (and it's inherent capacitance alone) is charged past the Vgs threshold and ends when Vgs is equal to the voltage of the gate driver.As you can see, if the MOSFET were not connected to a load and the drain instead tied to ground, there would be virtually no Miller effect since the drain can't "push against" the gate. It's already at minimum and won't move any further.Make sense?
The Miller effect being the reason for the Cascode amplifier configuration. The collector voltage stays relatively constant, so no Miller effect amplification of the Base-Collector capacitance.http://www.allaboutcircuits.com/textbook/semiconductors/chpt-4/cascode-amplifier/
International Recitifier is now owned by Infineon.That databook wouldn't happen to be Understanding HEXFET Switching Performance, would it?
MOSFET designers do a lot to reduce the Miller capacitance in devices, its not that important at low voltages.The plateau is where the channel is formed, basically - the charge in the gate mirrors the charges formingthe gate. Most of the channel area is protected from the drain voltage since the substrate is electricallyconnected to the source.There is, of course, still some drain-gate capacitance, but the total charge on the gate is much largerthan the charge on this capacitance in a good device.I did some experiments switching 3A with a drain voltage of 0.5V, 9V and about 25V on an STP3020Llogic-level StripFET, and the fall in drain voltage (blue) happens basically before the bulk of the gatecharge. The gate drive is an Arduino pin (so about 30 or 40 ohm source impedance)Note the horizontal scale is 25ns/div, vertical is 1V/div for yellow (gate voltage), 5V/div for drain(blue).The time taken to charge the plateau is extended for larger drain voltages, which suggests some sortof delayed Miller effect, but note the plateau is present even at a 0.5V drain voltage, when the Millereffect is for all purposes absent.Note also the sudden onset of drain voltage falling at the moment the plateau starts - clearly thisis when a channel first forms (the inversion layer)[ Note that due to the bench power supply and long leads I didn't get meaningful switch-off waveforms, and thinking about it I suspect the change of charge in the drift region is probably responsible for the delayed second part of the plateau - that change is proportional to the drain delta-V... ]