Myth Busters 3 – Myth: “You must have a gate resistor”

[MrAl]

Hi,

Couldnt help noticing this thread.  I wasnt able to read each and every post, but i see that the argument pro or con for having a gate resistor is based on the application of using an Arduino (like the Uno) to drive a MOSFET.  That makes the argument a little different than usual, because the usual argument is for a different reason.

The usual argument centers on the use of a series gate resistor in order to reduce oscillations that cause the MOSFET to turn on and off repeatedly while the source inductance path combined with various capacitances oscillates as an RLC circuit would when presented with a step input drive signal.  It oscillates for a time, then depending on the R value, starts to damp out toward steady state  Once steady state is reached, the circuit switch time period is considered over.
With no series R, we are left to the circuit's innate resistance that comes from a number of sources like the wire resistance.  This is often kept low in order to get high switching speed and high efficiency.  This in turn means that the RLC has low R to start with, and so oscillation is very very possible and in fact likely.
Adding a gate resistor increases the resistance and therefore the damping factor, and thus the oscillation becomes more damped and that means less oscillations.  The down side is slower switching speed, but that is a tradeoff that is often acceptable if not down right necessary.

With the Arduino pin drive application however the focus seems to be on the power dissipation of the internal Arduino pin circuit and since the chip already has some internal resistance the oscillation probably is not as much of a concern as long as the circuit is wired in a reasonable way.  But first and foremost we want to distinguish these two very different scenarios so that when we read about a gate resistor elsewhere we can be aware of what the context is, uC pin drive or concerns about problematic oscillations.

For the Arduino chip or any other uC chip, the signal at the gate will look like an exponential followed by a plateau, followed by another exponential.  During this time the internal pin circuit dissipates power.  The current is limited by the internal resistance, so the instantaneous power is always limited.   That means we can calculate the internal power dissipation and think about whether or not it would be damaging.

The two very different scenarios we would then encounter would be a slow PWM vs a high frequency PWM.  With the gate signal being repeated over and over again, the average power becomes a concern.  As the frequency goes up, the average power goes up, so there would be a limit on the frequency that could be used and still keep power dissipation in the pin circuit low enough to not damage the uC chip.  The local max power dissipation could be estimated as the specified max pin current times the measured voltage drop.  The chip has to be able to survive that or else it wont meet the pin specs.  Using that as a limit, we then calculate the total average power due to the switching waveform itself at the pin and then compare.  The power calculation would probably come from three intervals, the first exponential, the plateau, and the second exponential.  The total power can then be compared to the known max power and if it is lower than it should work, but if higher then there is a risk of damage over time.

 

[Boardburner2]

Hi,


The usual argument centers on the use of a series gate resistor in order to reduce oscillations that cause the MOSFET to turn on and off repeatedly while the source inductance path combined with various capacitances oscillates as an RLC circuit would when presented with a step input drive signal.  It oscillates for a time, then depending on the R value, starts to damp out toward steady state  Once steady state is reached, the circuit

 

Yes.
I am currently using a borrowed 2 GHz scope to do some tests.
Plenty of ringing on a breadboard circuit.
Not so on a soldered board with some thought to layout.

Many here are capable of building aerospace and medical equipment and doing the sums themselves.
Most i suspect are beginners who really only need advice on how to prevent destroying their (fairly expensive toys).
A 3 cent resistor would appear to be a reasonable solution. Bit of a generalisation though.
Semantics may be the problem. Stating that a gate resistor is required can fly in the face of a professional engineer but is possibly good advice for a beginner.

[MrAl]

Yes.
I am currently using a borrowed 2 GHz scope to do some tests.
Plenty of ringing on a breadboard circuit.
Not so on a soldered board with some thought to layout.

Many here are capable of building aerospace and medical equipment and doing the sums themselves.
Most i suspect are beginners who really only need advice on how to prevent destroying their (fairly expensive toys).
A 3 cent resistor would appear to be a reasonable solution. Bit of a generalisation though.
Semantics may be the problem. Stating that a gate resistor is required can fly in the face of a professional engineer but is possibly good advice for a beginner.

Hi,

That's great to hear, and i was also thinking we could estimate the chip pin wave as a ramp followed by a plateau followed by another ramp most likely.

But my post also mentioned how a gate resistor is OFTEN required for the purpose of reducing the ringing effect, and any good engineer who works on converters of any type that use mosfets would know this like the back of his/her hand :-)

International Rectifier gave a really good talk on this in one of their data books on HexFets, but i am not sure where that document is online anymore, or if it is online anymore.  I suspect it can be found on their website irf.com.

Do we have any consensus on what the equivalent series resistance of say the Uno chip pin has when going high?

[Boardburner2]

Do we have any consensus on what the equivalent series resistance of say the Uno chip pin has when going high?

Reading the thread i think the ESR is between 20 to 40 ohms.
Not had the chance to set up a suitable experiment though, BILLO i think tried it.
I have limited time with equipment , any suitable suggestions for experimentation ?

Hi,

That's great to hear, and i was also thinking we could estimate the chip pin wave as a ramp followed by a plateau followed by another ramp most likely.

Even if i understood that proprerly, it will probably take me a month to learn how to drive the machine.

[MrAl]

Reading the thread i think the ESR is between 20 to 40 ohms.
Not had the chance to set up a suitable experiment though, BILLO i think tried it.
I have limited time with equipment , any suitable suggestions for experimentation ?

Even if i understood that proprerly, it will probably take me a month to learn how to drive the machine.

Hi again,


Well now that you mention it an experiment would not be hard to do.
Ideally we would shoot for the whole load curve, but i think a four point test would suffice.

For example, load the high level logic state pin to 10ma, 20ma, 30ma, and 40ma, and read the voltage from pin to ground for each of those four current levels.  That would allow us to predict the response when the pin met up with a capacitor.  The internal resistance would then be:
R=(Vcc-Vpin)/i

where 'i' is the current at that point.

That test would give us four resistance values and we can see if it is nearly linear or not for one thing, and if not, just fit a curve to that data, then we can calculate a bunch of stuff with more certainty.

We also need to measure Vcc for each test point, or just measure the drop between Vcc and the pin.  Then R=Vdrop/i which is actually simpler.
I thought it would be good to know the output voltage at that point too though, and also the Vcc line at that point.  That would tell us a lot.

[krupski]

For the Arduino chip or any other uC chip, the signal at the gate will look like an exponential followed by a plateau, followed by another exponential.

I know I wasn't going to post in this thread anymore, but what you mentioned is worth a comment.

The two "exponentials" that you see have different causes.

The first one is due to the Miller effect combined with the inherent gate capacitance of the MOSFET. The "plateau" you see is when the drain is pulled as low as it's going to go, then finally the second exponential is the gate capacitance alone charging to Vgs equilibrium.

I don't think most people really know what the Miller effect is. Anywhere you look it up online, there are all kinds of formulas and hokey-pokey, but no clear explanation of the actual mechanism.

Imagine any 3 terminal (triode) device such as a BJT, a MOSFET and even a vacuum tube triode.

There is inherent capacitance that exists between each terminal and every other terminal, but the one that causes the Miller effect is the drain to gate capacitance (or collector to base, or plate to grid).

Imagine a MOSFET with the drain is being used to switch an LED on through the appropriate resistor.

Initially, the drain is at Vdd (minus the drop across the LED) and the gate is at 0.

Therefore, the inherent capacitor between the drain and gate is charged to Vdd - V-LED.

Now, begin to raise the gate voltage. As the MOSFET begins to turn on, the drain begins to lower, beginning to turn on the LED and also lowering the drain side of the inherent capacitor.

Of course, the gate side of the capacitor will also start to lower, which is FIGHTING the thing trying to drive the gate high.

The gate ends up looking like a LARGER capacitor which takes a lot of current to charge.

Once the MOSFET is saturated (that is, Vgs is at it's minimum), the "capacitance amplifying effect" stops and you get the plateau. Finally, you get another, less "severe" exponential as the gate (and it's inherent capacitance alone) is charged past the Vgs threshold and ends when Vgs is equal to the voltage of the gate driver.

As you can see, if the MOSFET were not connected to a load and the drain instead tied to ground, there would be virtually no Miller effect since the drain can't "push against" the gate. It's already at minimum and won't move any further.

Make sense?

[polymorph]

The Miller effect being the reason for the Cascode amplifier configuration. The collector voltage stays relatively constant, so no Miller effect amplification of the Base-Collector capacitance.

http://www.allaboutcircuits.com/textbook/semiconductors/chpt-4/cascode-amplifier/

[Jiggy-Ninja]

International Rectifier gave a really good talk on this in one of their data books on HexFets, but i am not sure where that document is online anymore, or if it is online anymore.  I suspect it can be found on their website irf.com.

Do we have any consensus on what the equivalent series resistance of say the Uno chip pin has when going high?

International Recitifier is now owned by Infineon.

That databook wouldn't happen to be Understanding HEXFET Switching Performance, would it?

[MarkT]

MOSFET designers do a lot to reduce the Miller capacitance in devices, its not that important at low voltages.

The plateau is where the channel is formed, basically - the charge in the gate mirrors the charges forming
the gate.  Most of the channel area is protected from the drain voltage since the substrate is electrically
connected to the source.

There is, of course, still some drain-gate capacitance, but the total charge on the gate is much larger
than the charge on this capacitance in a good device.

I did some experiments switching 3A with a drain voltage of 0.5V, 9V and about 25V on an STP3020L
logic-level StripFET, and the fall in drain voltage (blue) happens basically before the bulk of the gate
charge.  The gate drive is an Arduino pin (so about 30 or 40 ohm source impedance)





Note the horizontal scale is 25ns/div, vertical is 1V/div for yellow (gate voltage), 5V/div for drain(blue).
The time taken to charge the plateau is extended for larger drain voltages, which suggests some sort
of delayed Miller effect, but note the plateau is present even at a 0.5V drain voltage, when the Miller
effect is for all purposes absent.

Note also the sudden onset of drain voltage falling at the moment the plateau starts - clearly this
is when a channel first forms (the inversion layer)

[ Note that due to the bench power supply and long leads I didn't get meaningful switch-off waveforms, and thinking about it I suspect the change of charge in the drift region is probably responsible for the delayed second part of the plateau - that change is proportional to the drain delta-V... ]

[MrAl]

I know I wasn't going to post in this thread anymore, but what you mentioned is worth a comment.

The two "exponentials" that you see have different causes.

The first one is due to the Miller effect combined with the inherent gate capacitance of the MOSFET. The "plateau" you see is when the drain is pulled as low as it's going to go, then finally the second exponential is the gate capacitance alone charging to Vgs equilibrium.

I don't think most people really know what the Miller effect is. Anywhere you look it up online, there are all kinds of formulas and hokey-pokey, but no clear explanation of the actual mechanism.

Imagine any 3 terminal (triode) device such as a BJT, a MOSFET and even a vacuum tube triode.

There is inherent capacitance that exists between each terminal and every other terminal, but the one that causes the Miller effect is the drain to gate capacitance (or collector to base, or plate to grid).

Imagine a MOSFET with the drain is being used to switch an LED on through the appropriate resistor.

Initially, the drain is at Vdd (minus the drop across the LED) and the gate is at 0.

Therefore, the inherent capacitor between the drain and gate is charged to Vdd - V-LED.

Now, begin to raise the gate voltage. As the MOSFET begins to turn on, the drain begins to lower, beginning to turn on the LED and also lowering the drain side of the inherent capacitor.

Of course, the gate side of the capacitor will also start to lower, which is FIGHTING the thing trying to drive the gate high.

The gate ends up looking like a LARGER capacitor which takes a lot of current to charge.

Once the MOSFET is saturated (that is, Vgs is at it's minimum), the "capacitance amplifying effect" stops and you get the plateau. Finally, you get another, less "severe" exponential as the gate (and it's inherent capacitance alone) is charged past the Vgs threshold and ends when Vgs is equal to the voltage of the gate driver.

As you can see, if the MOSFET were not connected to a load and the drain instead tied to ground, there would be virtually no Miller effect since the drain can't "push against" the gate. It's already at minimum and won't move any further.

Make sense?

Hi,

Well that's an interesting read.

I do have to disagree slightly though, and i think it is only because you probably mis-spoke that's all.  The part is here:

StartQuote
Once the MOSFET is saturated (that is, Vgs is at it's minimum), the "capacitance amplifying effect" stops and you get the plateau. Finally, you get another, less "severe" exponential as the gate (and it's inherent capacitance alone) is charged past the Vgs threshold and ends when Vgs is equal to the voltage of the gate driver.
EndQuote

I agree that the Miller effect stops when Vds (not Vgs but that's probably a typo) is at it's minimum, but that is also when the plateau should end.  That's because the reason for the plateau in the first place is because the the Vds is falling and that provides feedback to the gate which ends up being held somewhat constant.

The way i like to explain the plateau is like a DC voltage regulator.  Imagine you want to hold the gate voltage perfectly constant for a short time, and you had to use the drain of the mosfet to do that.  The mosfet drain and associated capacitance acts like negative feedback, so when the drain voltage is falling you get feedback to the gate which holds it constant.  Of course once Vds falls completely you loose the negative feedback and so the gate is no longer regulated, so the plateau time is over and the gate voltage can start to rise again.

However, after taking a second look at the equivalent circuit, i see we mainly have to understand what happens at the drain rather than the gate, because the drain is what we see at the Arduino pin.  That's the main power consumer so we should turn our attention to that instead i think, and see what we can find.
I see some other posts now with some waveforms so i am going to take a look at that next.  If we get an Arduino scope pic we should be able to tell a lot about what is happening.

[MrAl]

The Miller effect being the reason for the Cascode amplifier configuration. The collector voltage stays relatively constant, so no Miller effect amplification of the Base-Collector capacitance.

http://www.allaboutcircuits.com/textbook/semiconductors/chpt-4/cascode-amplifier/

Hi,

Arent we talking about mosfets here though?

[MrAl]

International Recitifier is now owned by Infineon.

That databook wouldn't happen to be Understanding HEXFET Switching Performance, would it?

Hi,

Well the book i have is just the Hexfet data book, with blue cover.  It could very well be in that book too though.

[MrAl]

MOSFET designers do a lot to reduce the Miller capacitance in devices, its not that important at low voltages.

The plateau is where the channel is formed, basically - the charge in the gate mirrors the charges forming
the gate.  Most of the channel area is protected from the drain voltage since the substrate is electrically
connected to the source.

There is, of course, still some drain-gate capacitance, but the total charge on the gate is much larger
than the charge on this capacitance in a good device.

I did some experiments switching 3A with a drain voltage of 0.5V, 9V and about 25V on an STP3020L
logic-level StripFET, and the fall in drain voltage (blue) happens basically before the bulk of the gate
charge.  The gate drive is an Arduino pin (so about 30 or 40 ohm source impedance)





Note the horizontal scale is 25ns/div, vertical is 1V/div for yellow (gate voltage), 5V/div for drain(blue).
The time taken to charge the plateau is extended for larger drain voltages, which suggests some sort
of delayed Miller effect, but note the plateau is present even at a 0.5V drain voltage, when the Miller
effect is for all purposes absent.

Note also the sudden onset of drain voltage falling at the moment the plateau starts - clearly this
is when a channel first forms (the inversion layer)

[ Note that due to the bench power supply and long leads I didn't get meaningful switch-off waveforms, and thinking about it I suspect the change of charge in the drift region is probably responsible for the delayed second part of the plateau - that change is proportional to the drain delta-V... ]

Hi there,

Well the plateau (flat portion of the wave) will get more feedback from the drain for higher drain voltages, so that makes sense.

However as i was noting in another post, i think we should turn our attention to the drain circuit because that's really what we get at the Arduino pin, while the gate circuit probably does not consume as much power.  So understanding the drain vs load would probably be better.

Thus, testing with some resistors and if you want to use the scope and catch some turn on periods that might help too.  Once we know the voltage drop for various loads, that would tell us a lot.  I might be able to get to try this myself also.  In this way we should be able to tell what will happen with a capacitive load or mosfet gate load.

Oh i see what you did was use the Arduino to drive the mosfet.  That's good too, and if we can get the current flow at the time of turn on (and turn off) that would help calculate the internal power dissipation.
Any chance you could display the current out of the pin with those traces, especially the last one?

[MarkT]

I couldn't figure out an easy way to do that without a current probe, I can try adding a small series
resistance in the source, and I could engineer a better power source/load combination than flying leads
from a bench supply - or someone else can have a go.  Currently I have a cluster of croc-clips on the leads
of the TO220 package and its a bit of a crude lash-up, not impedance-controlled that's for sure!

[IamFof]

Hi guys

Thoroughly enjoyed this very informative thread.

Here are a couple of thoughts I've had.  In my professional career, I spent most of my time in development labs, working directly and in parallel with lots of very  clever EEs.  They, invariably, like me, tended to include a small gate resistor.  This thread has got me thinking as to where the gate resistor requirement came from.

Very many of you will never have come across the situation where it was obligatory to attach heat shunts to the legs of transistors, before applying a soldering iron.  Yes, when transistors first started to appear in commercial devices, this is what we had to do.  Ever hear of the expression "the fastest fuse on three legs"?  This is what transistors were commonly called, as they would die, just by looking at them the wrong way.  We used to joke that they were only there to protect the main fuse.

In these sort of scenarios, if I was a design engineer, I would use each and every form of insurance I could incorporate.  Don't forget that the development of transistors took quite a few years before one could (almost) guarantee many of the stated characteristics and parameters required for the design.

As FETs have always been the 'delicate' flower compared to BJT, due to potential for static damage, I suspect that the need for a gate resistor, might be a "folk memory", passed down by 'generations' of old farts like me, who have never had any need or reason to doubt the accepted wisdom.

Thanks for a great, educational read.

Fof