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### Topic: SPI - Rising, Falling; Leading, Trailing (Read 5387 times)previous topic - next topic

#### runaway_pancake

##### Jul 12, 2013, 03:05 am
I asked one the forum members about the information presented on his webpage regarding SPI, specifically Modes.

The Modes are described in terms of Rising and Falling edge and Leading and Trailing edge, too.

Mode 0 (the default) - clock is normally low (CPOL = 0), and the data is sampled on the transition from low to high (leading edge) (CPHA = 0)
Mode 1 - clock is normally low (CPOL = 0), and the data is sampled on the transition from high to low (trailing edge) (CPHA = 1)
Mode 2 - clock is normally high (CPOL = 1), and the data is sampled on the transition from high to low (leading edge) (CPHA = 0)
Mode 3 - clock is normally high (CPOL = 1), and the data is sampled on the transition from low to high (trailing edge) (CPHA = 1)

I'd thought that Rising and Leading were synonymous, Falling and Trailing likewise.

Our friend pointed me to a wikipedia entry on the matter.  So, is it that leading/trailing are relative to the "normal" (idle?) state of the clock?
If so, then why not not muddy the waters - and keep the discussion framed in terms of the low-going, high-going transitions?

[If it's a square wave (50-50), there is no "normal" state anyway, yes?]
"Who is like unto the beast? who is able to make war with him?"
When all else fails, check your wiring!

#### Grumpy_Mike

#1
##### Jul 12, 2013, 03:22 am
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[If it's a square wave (50-50), there is no "normal" state anyway, yes?]

Yes but in this context normal means the state of the clock when there is not a transfer going on.

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I'd thought that Rising and Leading were synonymous, Falling and Trailing likewise.

Yes I think they are as well.

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and keep the discussion framed in terms of the low-going, high-going transitions?

You want it to be too easy?

#### SurferTim

#2
##### Jul 12, 2013, 04:07 am
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I'd thought that Rising and Leading were synonymous, Falling and Trailing likewise.

If the leading edge is the first transition, and the trailing edge is the second, then they are not synonymous. If the clock is HIGH with LOW pulses (SPI modes 2 and 3), the leading edge would be a negative transition, and the trailing edge would be a positive transition.

#### 1ChicagoDave

#3
##### Jul 12, 2013, 05:23 pm
Another way of explaining it (very similar, & not necessarily better, but may help others reading this post?) could be --

For a +ve edge triggered design +ve (or rising) edge is called 'leading edge' whereas -ve (or falling) edge is called 'trailing edge'.

For a -ve edge triggered design -ve (or falling) edge is called 'leading edge' whereas +ve (or rising) edge is called 'trailing edge'.

If you can relate it to "sine wave" terms, it all depends on which point marks the beginning of the "period". Sort of how SIN waves & COS waves are basically the same. They just begin at different values (0 vs 1).

Great question!

#### runaway_pancake

#4
##### Jul 13, 2013, 02:18 am
Well, OK, relative to the normal (idle) state it is, I guess.  I'm unfamiliar with it be framed that way.
I will (continue to) keep with low-to-high ["positive going"] and high-to-low ["negative going"].
For me, when it's about an edge-triggered event, so long as low is low and high is high, all I've ever cared about is what's supposed to happen on account of that transition.

I think that I've only seen trouble where:

• idle wasn't idle long enough or

• the period following the transition was too brief

"Who is like unto the beast? who is able to make war with him?"
When all else fails, check your wiring!

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