Hi Riva,
The Pedevide ADC library is considered the standard ADC library for Teensy. Users are extremely unlikely to get at ADC features such as differential-mode reads unless they delve into specific registers and enjoying the cryptic (at best!) Freescale datasheets re: how to program the thing.
The Pedevide ADC library is hosted on Github and is installed as part of the Teensyduino package. Thus, if you have a relatively recent sample of the Teensyduino install, you should find it, along with lots of examples. Updating your test is as simple as including the Pedevide library and then using the library commands to do the sequential reads, and so on.
Is this a fair comparison? The answer of course is yes and no. The library enables things like sequential reads that for whatever reason the Arduino IDE does not support using standard commands. Ditto for digitalReadFast, etc. These sorts of standard commands for Teensy are not necessarily part of the the usual Arduino universe thanks to decisions by the higher-ups here. I can see their motivation (keep it simple) but that can get in the way of maximum performance.
Additionally, you need to specify carefully what your source is. For example, the marketing department at Freescale assumes a 8-Ohm source, external caps on the inputs, etc. I presume that Atmel has similar sets of recommendations on how to optimize the input stages.
Here are some comments from Pedevide in the ADC library with benchmarks for the LC and 3.x series that may be of interest. Note how the Teensy 3.x series can achieve 'legal' sampling speeds of 500kHz, assuming you have a very good signal source. Under default circumstances (i.e. 10bit ADC, 4x oversampling, MED conversion speed) the benchmarks indicate about 17us per conversion. Digital "fast" reads and writes go into the Megahertz range. If there is interest, I can try and dig those up also.
RESULTS OF THE TEST Teensy 3.x
Measure continuously a voltage divider.
Measurement pin A9 (23). Clock speed 96 Mhz, bus speed 48 MHz.
Using ADC_LOW_SPEED (same as ADC_VERY_LOW_SPEED) for sampling and conversion speeds
ADC resolution Measurement frequency Num. averages
16 bits 81 kHz 1
12 bits 94 kHz 1
10 bits 94 kHz 1
8 bits 103 kHz 1
16 bits 2.5 kHz 32
12 bits 2.9 kHz 32
10 bits 2.9 kHz 32
8 bits 3.2 kHz 32
Using ADC_MED_SPEED for sampling and conversion speeds
ADC resolution Measurement frequency Num. averages
16 bits 193 kHz 1
12 bits 231 kHz 1
10 bits 231 kHz 1
8 bits 261 kHz 1
10 bits 58 kHz 4 (default settings) corresponds to about 17.24 us
Using ADC_HIGH_SPEED (same as ADC_HIGH_SPEED_16BITS) for sampling and conversion speeds
ADC resolution Measurement frequency Num. averages
16 bits 414 kHz 1
12 bits 500 kHz 1
10 bits 500 kHz 1
8 bits 571 kHz 1
8 bits 308 kHz 1 ADC_VERY_LOW_SPEED sampling
8 bits 387 kHz 1 ADC_LOW_SPEED sampling
8 bits 480 kHz 1 ADC_MED_SPEED sampling
8 bits 632 kHz 1 ADC_VERY_HIGH_SPEED sampling
Using ADC_VERY_HIGH_SPEED for sampling and conversion speeds. This conversion speed is over the limit of the specs! (speed=24MHz, limit = 18 MHz for res<16 and 12 for res=16)
ADC resolution Measurement frequency Num. averages
16 bits 888 kHz 1
12 bits 1090 kHz 1
10 bits 1090 kHz 1
8 bits 1262 kHz 1
At 96 Mhz (bus at 48 MHz), 632 KHz is the fastest we can do within the specs, and only if the sample's impedance is low enough.
RESULTS OF THE TEST Teensy LC
Measure continuously a voltage divider.
Measurement pin A9 (23). Clock speed 48 Mhz, bus speed 24 MHz.
Using ADC_VERY_LOW_SPEED for sampling and conversion speeds
ADC resolution Measurement frequency Num. averages
16 bits 33.3 kHz 1
12 bits 37.5 kHz 1
10 bits 37.5 kHz 1
8 bits 40.5 kHz 1
16 bits 1.04 kHz 32
12 bits 1.2 kHz 32
10 bits 1.2 kHz 32
8 bits 1.3 kHz 32
ADC_LOW_SPEED, ADC_MED_SPEED, ADC_HIGH_SPEED_16BITS, ADC_HIGH_SPEED and ADC_VERY_HIGH_SPEED are the same for Teensy 3.x and LC, except for a very small amount that depends on the bus speed and not on the ADC clock (which is the same for those speeds). This difference corresponds to 5 bus clock cycles, which is about 0.1 us.
For 8 bits resolution, 1 average, ADC_MED_SPEED sampling speed the measurement frequencies for the different ADACK are:
ADC_ADACK_2_4 106.8 kHz
ADC_ADACK_4_0 162.6 kHz
ADC_ADACK_5_2 235.1 kHz
ADC_ADACK_6_2 263.3 kHz
For Teensy 3.x the results are similar but not identical for two reasons: the bus clock plays a small role in the total time and the frequency of this ADACK clock is acually quite variable, the values are the typical ones, but in the electrical datasheet it says that they can range from +-50% their values aproximately, so every Teensy can have different frequencies.