At least for access to RAM, they both do have the AHB-AP component. At least that part comes from ARM, so it's likely to be the same.
But even then, many thorny details can get in the way. For example, in the Freescale chip you can access the MDM-AP and even the AHB-AP while the chip is in reset mode. But Freescale's bus matrix obeys the reset and won't work at all. So if you want to get to anything that can't be reached directly inside the ARM core or through the core's private peripheral bus, you have to go through quite a lot of work to configure the debug unit to catch the reset vector and put the chip into halt mode before it can start, just to be able to release reset and gain access to everything else (like the RAM) which lies on the other side of that bus matrix.
I honestly haven't fiddled with Atmel's ARM chips much. But years ago I did play with the NXP LPC2000 ones (long before NXP acquired Freescale, both of whom are about to be acquired by Qualcomm). The LPC chips were riddled with other gotchas. One particularly difficult problem was they put the GPIO onto the AHB to avoid the high latency in whatever bus bridge they were using back then, but they added some (undocumented) bug where it wouldn't properly ignore bus cycles during debug mode. At the time I found an ugly workaround, but didn't continue farther with those chips since Freescale was soon to release the first ones with DSP extension and a good DMA controller.
Probably very few people outside of IAR, Segger and maybe the OpenOCD devs ever know of these internal chip issues....