Go Down

Topic: Issues Compiling Goertzel Sketch (Read 1 time) previous topic - next topic

rickso234

Quote
Yes it can go faster if you twiddle with the ADC clock or put it in free running mode.
You can change the ADC clock by changing the ADC prescaler, ADPS2,1,0, correct? If default prescaler is 128 and the prescaler is set to 16 by ADPS2,1,0, then the sampling rate increases by 128/16 or 8 times?

In some FHT code, assuming the default rate was 9600Hz and changing the prescaler from 128 to 64 and 32 for rates of 19.2kHz and 38.4kHz respectively, gave exactly the expected bin spacing based on a defined N point FHT. Bin spacing was determined by generating tones at the expected bins and observing a change in value at that bin. If the default "prescaler = 128" sample rate were really 8900, then wouldn't the bin spacing be something different?

These are the bin widths I'm seeing given the expected sample rate (SR), the resulting bandwidth (BW) of SR/2, and a #Bins FHT:

SR(Hz)   BW   #Bins  Bin Width(Hz
-------   ------   ------   --------
9,600     4,800   32     150
19,200   9,600   32     300
38,400 19,200   32     600
      
9,600     4,800   64       75
19,200   9,600   64      150
38,400 19,200   64     300
      
9,600     4,800   128      37.5
19,200   9,600   128       75
38,400 19,200   128     150


Grumpy_Mike

#16
Aug 18, 2016, 02:28 am Last Edit: Aug 18, 2016, 02:28 am by Grumpy_Mike
Quote
These are the bin widths I'm seeing given the expected sample rate (SR), the resulting bandwidth (BW) of SR/2, and a #Bins FHT:
Yes if you are seeing those bin widths that is indeed correct.

Go Up