About the bypass caps, do you think it may be the source of the issue?
so it's not easy to add that much caps on them
Also, you must have a 1.0uF bypass cap for each chip,
but you say 0,1uF and Paul says 1,0uF so i don't realy know which to buy.
What i am doing right now is removing all the TPIC chips and puting them back one by one to understant at what point the problem starts.
I would use 0.1uF ceramic capacitors.
My problem now is when i send datas in order to open drain x, it opens drain x+1 instead. When a try to open last drain (n°7) of a TPIC chip, if opens drain 0 from next TPIC chip.Depending on if i use one, two or zero 74HCT04 chip, the issue starts from a different TPIC chip. I will try to draw a schematic but it is quite large et and made a lot of changes for testing purpose
i'm pretty sure these buffers apply a tiny delay
i would have known about these evil capacitors
But that delay is insignificant compared to the delay caused to the data line by passing through a dozen shift register chips!
It is not the capacitors that are evil, they are your friends, they combat the evil.
What size (gage) wire are you using for +5 and Gnd?