Parallel library for Due External Memory Bus/Static Memory Controller

[stimmer]

I just bought a DigiX (a Due clone, see https://www.kickstarter.com/projects/digistump/digix-the-ultimate-arduino-compatible-board-with-w and http://digistump.com/wiki/digix ). The DigiX has the four missing address and data pins (among others) on another row of connectors to the right of the board. Unfortunately, for compatibility with the Due the NRD signal is still wired to A5 so is unusable - although as I pointed out before you don't usually need it.

I wired up my 128Kx8bit ram up to the DigiX, and can confirm that the library works correctly with no modification needed, and no address gaps I haven't tried a 16 bit data bus yet as I haven't got a 16 bit ram, but I can't think of any reason why it wouldn't work.

[graynomad]

How can there not be a gap and duplication with A5 missing? Or is it me that's missing (something

If you write 0-255 sequentially into the first 255 locations do you read 0-255 back?

_____
Rob

[stimmer]

I worded it confusingly - what I meant was NRD is unusable, not A5. With them both wired to the same Due pin it's either one or the other. But NRD is not needed for a RAM.

My test program writes all 128K sequentially with a pseudorandom sequence then reads it all back checking every value - no errors

[graynomad]

Yeah ok, that makes sense.

______
Rob

[LMI1]

If address pins are missing you will have holes in the space that would cause duplications on top of other data.

So for example if A4 was missing you could write 16 contiguous bytes ok, but the 17th byte will go into location 0, thus overwriting the first byte. This could be manageable but a right PITA.

Likewise with data, the top bits may not matter if you stick to values below the first missing bit, but if you are missing any low-order bits you will be in trouble. This is almost not possible to use unless you "adjust" every variable you save and "unadjust" every variable you retrieve.

______
Rob

I don't think missing address pins cause other problems than a smaller device. For instance a 65000 byte device with 16 address bits. If leave one address pin/bit out, you'll have a device with 32000 usable bytes. If it is a some kind of rom and you connect it to a processor with all address pins, then you'll get gaps (or a great mess, if don't take care). I am not going to draw any truth tables so I leave this here.

[pito]

You may connect the 8MB ramdisk to your DUE via the External Memory Bus (Static 8bit memory) - http://forum.arduino.cc/index.php?topic=220918.0

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RDisk DUE (EMB signal names)
================
D0-D7 D0-D7
NWR NWE
NRD NRD
NDATA Ax

With Ax = 1 you write the 24bit starting address of a block
With Ax = 0 you write/read the bytes sequentially from the address

[pito]

There is an undocumented feature in the driver with

Code: [Select]

PARALLEL_CS_NONE parameter
It causes 12ns timing for NRD/NWE regardless any other timing settings (verified with LA).

Also I do not understand the elapsed time results for the test sketch, where I write/read 1 mil bytes with the same elapsed time for quite different EMB timings:

Code: [Select]

// Configure parallel bus for 8bits, no CS, A0, and NRD and NWE
Parallel.begin(PARALLEL_BUS_WIDTH_8, PARALLEL_CS_1, 1, 1, 1);
// Configure bus timings.. EXPERIMENTAL
Parallel.setAddressSetupTiming(1,1,1,1);
// NWE, NCSWE, NRD, NCSRD  - we do not use NCSs
Parallel.setPulseTiming(4,1,7,1);
Parallel.setCycleTiming(6,9);

START OF THE TEST
WRITING BYTES TO RAMDISK
READING BYTES FROM RAMDISK
SUM = 234000000
ELAPSED WRITE = 680 msec
ELAPSED READ = 846 msec
TEST STOP

// Configure parallel bus for 8bits, no CS, A0, and NRD and NWE
Parallel.begin(PARALLEL_BUS_WIDTH_8, PARALLEL_CS_1, 1, 1, 1);
// Configure bus timings.. EXPERIMENTAL
Parallel.setAddressSetupTiming(1,1,1,1);
// NWE, NCSWE, NRD, NCSRD  - we do not use NCSs
Parallel.setPulseTiming(7,1,7,1);
Parallel.setCycleTiming(9,9);

START OF THE TEST
WRITING BYTES TO RAMDISK
READING BYTES FROM RAMDISK
SUM = 234000000
ELAPSED WRITE = 680 msec
ELAPSED READ = 846 msec
TEST STOP

with the sketch from http://forum.arduino.cc/index.php?topic=220918.msg1718934#msg1718934
(you may run the sketch without the ramdisk attached).

PS: with 12ns+48ns+12ns=72ns write cycle I would expect faster write than above 680ns per byte. Does it mean the driver (inclusive the "for loop") creates a 610ns overhead??

[pito]

Another issue I cope is the NWE timing does not react to NWE pulse setting properly.

Parallel.setPulseTiming(7,1,7,1);

For example doubling the setting (with adjusting the CycleTiming accordingly) does not change the total elapsed time for write. It seems the NRD setting works.

[pito]

I did a measurement of the actual NWE signal High/Low durations during the 1mil write "for loop" vs. the NWE timing parameters settings (the resolution of my LA is 5ns):

Code: [Select]

A, P, C L H L+H MBytes/sec
========================================================================
1, 2, 4 25 205 230 4.35
1, 4, 6 45 180 225 4.44
1, 8,10 95 135 230 4.35
1,16,18 185 40 225 4.44
1,32,34 380 25 405 2.47

where
A - NWE setAddressSetupTiming
P - NWE setPulseTiming
C - NWE setCycleTiming
L[ns] - NWE active low pulse (write pulse)
H[ns] - overhead of the for..loop

How to decipher that results?? Any hint?
Why the L+H is constant for P=2 or 4 or 8 or 16?

[rcalix1]

Hello,

I read your Parallel library this afternoon and think it is very close to what I need. I have an Arduino Due board and a PGA69-CM1K co-processor. I am using this chip to do machine learning work. I have connected the Due board to the CM1K and can perform my analysis. However, I am currently using I2C to send the data. This approach is very slow and it affects my performance. So, what I need to do now is to send the data in Parallel (16 bits preferably although 8 bits would do for now). Could you tell me if you think this is possible with the library that you have. I noticed that some aspects appear to be very specific to the external memory device you are using. Any suggestions and advice on this would be greatly appreciated.

The spec of the chip I am using is here:http://www.cognimem.com/_docs/Technical-Manuals/TM_CM1K_PGA69_Hardware_Manual.pdf


Also, I tried compiling the library but it gave me an error that it could not find the "sam.h" file.

Thanks
Ricardo

[EvIl_DeViL]

what about taijiuino R3?

I saw here you're complaining about
D8 PC10
D9 PC11
A6 PC27
which are all broken out on taijiuino with many other pins as you can see in my previous link.

The only issue is PC26 (PWM4) which is still wired to PA29. It seems because they're trying to keep compatibility with mega shields as MarkT says here

would a taijiuino be enough to drive a SDRAM like this?

[MANIBMT]

HI ,

I need LCD library for Arduino due.i don't where i get it.Any one can help me .

[jlsilicon]

I didn't use NRD, I just tied the OE pin low (a write cycle still works with OE low - OE is active low)

- Makes sense to just tie the OE as High.

But, A6 is ignored / dropped out.
- Maybe (A6  PC27  N/C) can be soldered Manually Hotwired onto the Chip ?

I did not see any suggested RAM Chips.  The Chip need to be 3V - correct ?

Does anyone have a Diagram for this wiring ?