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Topic: FPGA programming and JTAG (Read 4067 times) previous topic - next topic

DarioPennisi

Hi Julian,
The tool to convert fpga images is coming very soon but first we have to release a bit more stuff such as software drivers running on embedded processor to drive the up blocks we already released.
The hint I can give you is that the ttf needs to be bit reversed as quartus generates them in the opposite bit endianness required by the flash. Note also that along with the fpga bitstream we are also including nios firmware run in place from flash. Btw if you just bit reverse the ttf from quartus you should be able to immediately load your fpga but it won't help much to integrate with our sw infrastructure unless you plan to just use JTAG bridge directly connected to peripherals, thus bypassing the RPC mechanism we set up.
I would ask to be patient as we're scrambling to solve a few issues we had with the early sw release and we're trying to ease the experience for those who want to deal with fpga directly. As I mentioned somewhere else we are dealing with Intel to have the possibility to push some sw to enable USB blaster emulation via SAMD21 and some modifications we made to IP blocks to make them work more efficiently.
Thank you for your patience...

awtem

Hi Dario,

thanks a lot for your pointers! Indeed, flipping the bits did the trick :-)  With this change, I have now successfully uploaded and tested my own blinky-LED-FPGA image :-)

But you are right, things would be much easier and more fun, if the USB-Blaster emulation would be available. Until this is available, I guess I will have to be patient...

Thanks again & best regards!

RayL

Dario;
I have recently been made aware of the Vidor 4000 and a friend of mine thinks it may be the tool we need in our efforts to investigate the CDMA communications between our Model Trains and their controller.

I have been reading the posts regarding the Vidor 4000 and I noticed you mention there are currently no tools for programming the FPGA.

You also mention Quartus.

I have recently been using a CPLD development board at school from RSR Electronics (PLDT2) and the Altera EPM7128SLC84 CPLD chip on the board.

The software I downloaded is Quartus II v7.2 SP3. I run it on a PC under MS Windows XP or Win7.
The PCs I use have a parallel port, which is what the PLDT2 wants to connect to.

Can I use my Quartus v7.2 SP3 setup to program the FPGA on the Vidor 4000?
Thanks
Ray

DarioPennisi

Hi Ray,
You can use quartus along with USB blaster but you will need a more recent version of quartus that supports cyclone 10 lp.
In order to use USB blaster ( or byte blaster if understand correctly) then you would need to mount the JTAG header on the board.
I would not however recommend going this route. We are about to release a sketch that allows sam d21 to emulate USB blaster so you could directly program fpga from Vidor USB connector. Actually if you look at the procedure to restore fpga boot image you will see that the first step loads a sketch that allows second step to upload a svf file as generated by quartus. The sketch is not USB blaster compatible but would do the job if you just want to load the fpga in ram. Elsewhere you will see someone successfully loaded in flash his own image manipulating ttf files generated by quartus but once again I would not recommend this as we're about to release the full flow for this.
The reason why it's taking a while to release these tools is that first if all we need to settle some legals with Intel and secondly we want to polish them a bit more to avoid issues.
Stay tuned...

a2retro

Hi Dario, what is the update on this?

DarioPennisi

Almost there. legals are a nightmare but looks like in principle we have it sorted out. we're just waiting for some paperwork to be signed, which unfortunately does not necessarily means it's going to be tomorrow.
be sure we're on top of it.

ClockFabric

Really excited for this to come out!

DarioPennisi

Hi TC,
Neopixels are already there and they support gfx library so you can draw shapes and text on them without loading the processor.

Julian,
Regarding ttf it needs to be bit reversed. For the length it may also include nios software as we load it just after the fpga image. The tool to do this is going to be published very soon.

viraniac

#23
Oct 02, 2018, 09:56 am Last Edit: Oct 02, 2018, 10:00 am by viraniac
Hi Dario,

I also purchased the vidor 4000 to learn FPGA programming. Seeing that usb blaster emulation is not supported yet is bit of a let down.

I went to https://www.arduino.cc/en/Reference/Libraries to check the details about the VidorPeripherals library but its not listed there. Is there a documentation for it somewhere that I can refer to?

Also if you can share where I can look into the source code of these libraries that will be great. I think that can help me to see if I can make a custom FPGA library as per my needs.

Thanks & Regards

DarioPennisi

#24
Oct 02, 2018, 03:52 pm Last Edit: Oct 02, 2018, 03:52 pm by DarioPennisi
Hi,
source code for IP blocks and arduino libraries are here: https://github.com/vidor-libraries/

viraniac

I have looked into the vidor-libraries/vidorFPGA repository. In the readme it says that we can use Quartus to generate ttf file and then have to do some post processing. However there is no information on what needs to be done.

Is there any links for the same?


fphiggins

Is the emulated USB Blaster via SAM D21 available yet? It would seem that there wouldn't be any proprietary IP needed for this.

Thanks,
Frank Higgins

foxrobotics

Is the emulated USB Blaster via SAM D21 available yet? It would seem that there wouldn't be any proprietary IP needed for this.

Thanks,
Frank Higgins
I second this. We've been asked to wait a "few days" over and over again and it's been months. Is there any way we could get a transparent answer on when full FPGA support, be it through web services or through a tutorial and a sketch will be available?

DarioPennisi

Hi guys,
i'm sorry i keep delaying this but there are a few issues:
1) we are working to release a new source tree with a nice autodetection mechanism of what is in the FPGA and along with it we're producing the related documentation. it turned out a bit more lengthy than forecasted also because we had a few things in the middle (maker faire in Rome and others).
2) although USB blaster has been reverse engineered and it's mechanics are open source, as a company we can't publish it until we have the proper paperwork in place and this is taking a while. unfortunately things that are awfully simple become quite complicated when you go through legal offices of a big company. believe me when i say we're pushing like mad...
maybe if this doesn't work out shortly "someone will randomly post it out in the wild"... who knows (i bet you get what i mean!)

thanks for your patience!

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