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Topic: FPGA programming and JTAG (Read 6813 times) previous topic - next topic


Aug 20, 2019, 11:37 am Last Edit: Aug 20, 2019, 11:51 am by Biblioman
What happens with this project? Where is the web-based user interface that allows you to assemble your combination of IP blocks?


Nov 11, 2019, 10:53 pm Last Edit: Nov 12, 2019, 09:28 pm by jordanf2012

Is there any documentation on how the data is passed between the SAM C++ program and the FPGA JTAG?

I understand that the FPGA JTAG bridge acts as an Avalon master and one could use it to access the peripherals, but I cannot find a good source of information.  Unfortunately there are no comments in the code, which makes it really hard to re-use.

I would like to use the board with my own FPGA peripherals.

I have over 10 years of experience with Quartus (9, 11, 16 and 18) with Acex, Cyclone II, Cyclone IV, Cyclone 10 and MAX10, besides NIOS applications.

So if you could point me to the direction of how you implemented the mailbox mechanism and how to use it, I would be really happy.

Thank you in advance.


Did you check with project sources in VidorBistream repository?

There are docs (AsciiDoc format) for jtag_bridge and mailbox hardware parts, explaining what it does.

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