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Topic: FPGA bitstream and header (Read 905 times) previous topic - next topic

philippe_at_sysemb

It's very frustrating to have a board with a FPGA and not being able to play with it.

I know that a wrong configuration of FPGA I/O could lead to board destruction.
But we already have quartus files with I/O configuration so risks are less.
And if I have well understood the architecture :  if we don't play with first 512KB of flash (factory application) it will always be possible to return in boot process, so to download a new bitstream.

My problems now are :
- I don't know if quartus ttf output file is exactly the same to be upload with the sketch.
- I don't know how to calculate length and checksum for the header (signature) file.
The lenght define in the header seems not to be equal to ttf lenght.

I would like to have the exact process to transform a very simple quartus project (even simply a link between two SAM GPIO) to signature+ttf.

Thanks a lot

DarioPennisi

Hi Philippe,
actually also if you play with the first 512K of flash you will be able to recover as SAM has a jtag connection and Sandeep was kind enough to provide a fpga boot image recovery tool so whatever happens you won't brick the board.
quartus ttf file is not the same ttf file we're providing with the library. as you may read somewhere else if you want to load your ttf you need to bit reverse it as quartus does not produce bits in the right order for the flash. also, the ttf we produce includes also elf files from NIOS in case it runs code from flash (to avoid wasting internal RAM which is limited). we have a tool that produces the required files/headers from the input but it's taking a while to release because we need to perform some more testing and, as i wrote a few times, we initially wanted to prioritize support to the usage of the precompiled librabries.
i see that several other people is looking to get access to FPGA so i'll try to expedite the release process. in these days i'm also working to package the full source for the graphics fpga so that it can be released so stay tuned. i guarantee that your patience will be rewarded.

sbielmann

Hello Dario,

will you post the availability of this package and documentation here in this forum or else where ?

Stephan

DarioPennisi

Hi Stephan,
See here: https://forum.arduino.cc/index.php?topic=562465.msg3857337#msg3857337

sbielmann


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