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Topic: LED Blinky test SAMD21 vs FPGA (Read 277 times) previous topic - next topic

mphillips53

Aug 05, 2018, 11:51 pm Last Edit: Aug 06, 2018, 12:18 am by mphillips53
I attached a led to pin A1 and ran the following test:
Code: [Select]
void loop() {
  // Test SAMD21 side
  Serial.println("Testing SAMD21 side...");
  pinMode(A1,OUTPUT);
  digitalWrite(A1,HIGH);
  delay(500);
  pinMode(A1, INPUT);
  Serial.print("SAMD21 Pin A1 is ");
  Serial.println(digitalRead(A1) == LOW ? "LOW" : "HIGH");
 
  pinMode(A1,OUTPUT); 
  digitalWrite(A1,LOW);
  delay(500);
  pinMode(A1, INPUT);
  Serial.print("SAMD21 Pin A1 is ");
  Serial.println(digitalRead(A1) == LOW ? "LOW" : "HIGH");   

  //Test FPGA side
  Serial.println("Testing FPGA side...");
  FPGA.pinMode(FPGA_A1,OUTPUT);
  FPGA.digitalWrite(FPGA_A1,HIGH);
  delay(500);
  FPGA.pinMode(FPGA_A1, INPUT);
  Serial.print("FPGA Pin A1 is ");
  Serial.println(FPGA.digitalRead(FPGA_A1) == LOW ? "LOW" : "HIGH");
 
  FPGA.pinMode(FPGA_A1,OUTPUT); 
  FPGA.digitalWrite(FPGA_A1,LOW);
  delay(500);
  FPGA.pinMode(FPGA_A1, INPUT);
  Serial.print("FPGA Pin A1 is ");
  Serial.println(FPGA.digitalRead(FPGA_A1) == LOW ? "LOW" : "HIGH");   
}


I got the following results:
Testing SAMD21 side...
SAMD21 Pin A1 is HIGH
SAMD21 Pin A1 is LOW
Testing FPGA side...
FPGA Pin A1 is LOW
FPGA Pin A1 is LOW
Testing SAMD21 side...
SAMD21 Pin A1 is HIGH
SAMD21 Pin A1 is LOW
Testing FPGA side...
FPGA Pin A1 is LOW
FPGA Pin A1 is LOW

Why can't I read this pin correctly from the FPGA side?  By the way, the led does blink!


sandeepmistry

Hi @mphillips53,

Thanks for the report! We've added it to out internal list of things to look at, we'll report back once we have some news ...

DarioPennisi

hi,
i may be wrong but i see a major issue with this code. if you set pin as input who is going to drive it?
on the SAMD part of the code you may see the "old" state just because pin read is very fast and the floating input does not have time to change value however since FPGA pins are handled indirectly it takes more time between direction change and readback so it has time to get to the value of the internal pulls.

i would suggest you set the pin as input on FPGA and output on SAMD or vice versa and drive the pin from one side and read from the other. this way you can be sure that the line is firmly driven when being read.

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