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Topic: vidor ip and avalon interface (Read 509 times) previous topic - next topic


I am curious about the interaction between SAMD and FPGA ip cores.

It looks like that the ip cores in https://github.com/vidor-libraries/VidorFPGA use Intel avalon interface and configured as avalon ip cores (with _hw.tcl files). 

I presume that there must be a Nios II processor that functions as an "i/o processor" and SAMD accesses them via the Nios.  Is this correct? 



Correct. And not only there's a nios, it also runs drivers that programs device so that samd just needs to send high level commands to fpga and those are executed by nios.
We are about to release full source code for this so that you can reuse our drivers and infrastructure for your blend of fpga image

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