Go Down

Topic: How to code and run VHDL examples? (Read 3088 times) previous topic - next topic

justchris

Hi,

I'm very new on FPGA and would learn how to code VHDL on the new Arduino MKR Vidor 4000. So I'm searching for a step by step tutorial how to setup an IDE where I can code simple Logic Elements in VHDL like an AND element or things like that. Additionally it would be nice to simulate VHDL before sending the bitstream to the real hardware. The only examples I found are in C and all VHDL is hidden in Libs, so I can't learn how to code an FPGA.

DarioPennisi

Well, the road is long and winding however there are a few pointers I can suggest:

https://forum.arduino.cc/index.php?topic=563495.0

https://plan.seek.intel.com/PSG_WW_NC_LPCD_FR_2018_FPGAforDummiesbook

And finally a tutorial I wrote but for verilog:

https://www.arduino.cc/en/Tutorial/VidorHDL

justchris

#2
Dec 09, 2018, 07:12 pm Last Edit: Dec 09, 2018, 07:17 pm by justchris
Thanks for your effort. I hope this will help me to get into the miracle of VHDL with an Adruino board.

As a newcomer to FPGA it would be nice to have a step by step tutorial, where I can build simple logic thinks with VHDL and the arduino board. Libs are fine, but does not help me learning to programming an FPGA.

justchris

Can I write my own VHDL or SystemVerilog Code in the Arduino IDE? Could I simulate my program before I transfer the bitstream to the real FPGA? The community are tiny at this moment for the Arduino FPGA. I hope this would grow over the next months.

DarioPennisi

Hi, hdl actually is not supported in Arduino ide. For that you have to work directly with quartus and you can simulate it using modelsim, shipped with quartus installation. This is not something for beginners and I suggest you go down this path only if you are really determined. On Intel web site there are lots of tutorials and free online training courses about almost any aspect of quartus and modelsim however the learning curve is a bit steep...

As you probably read we are actually trying to make this easier by providing ready made IP blocks and project templates.
At the moment we're not providing an easy way to simulate a custom block but this for sure is something we may work on in the near future.

Thanks,

Dario

justchris

Ok thanks for your explanation. I have an german ebook called "FPGA for Maker" for beginners and here it will start with VHDL and the IDE Vivado. My goal is to try out these very simple examples(LED switch, Test logic Gates with two switches and a LED etc.) on the Arduino FPGA. I thought Arduino were good for learning VHDL or Verilog. I think that was my fail.

My wish was to enter something like this,with the constraints file and run ist on the Arduino, with two hardware buttons und one led connected. One total simple task for an absolute FPGA beginner like me, but with the Arduino this task isn't simple, but it should in my opinion. 
Quote
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_logic is
   Port ( in_1 : in STD_LOGIC;
          in_2 : in STD_LOGIC;
          out : out STD_LOGIC;);
end simple_logic;

architecture impl of simple_logic is

begin
   out_and <= in_1 and in_2;
end impl;

cord_elias

Hi,

you can run the VHDL examples from my book "FPGAs for Makers" on Vidor 4000.
Just follow the hints given in appendix "C" with regard to application of "Quartus  Prime Lite" instead of "Vivado".

You need to assign placement constraints which are specific to Vidor 4000.
With regard to the quoted simple and gate implementation:
If you connect switches to Vidor MKR pins 8 and 7 and a LED to pin 6 you need these placement assignments (which can be extracted from the Vidor 4000 schematic, see https://store.arduino.cc/arduino-vidor-4000):
in_1 ->  F16 ("SAM_PORTS.PA16")
in_2 ->  G15 ("SAM_PORTS.PA21")
out_1 -> G16 ("SAM_PORTS.PA20")

Follow the workflow as described in the book up to bitstream generation (.sof file).
Before you can use Quartus programmer tool to download the bitstream into the configuration SRAM of the FPGA, download the "USBBlaster" sketch (get it  from https://github.com/vidor-libraries) via Arduino IDE to Vidor 4000. When completed successfully the board appears to teh programmer as "regular" FPGA board with a Cylcone 10LP device and you can proceed with the usual process and download the bitstream as you would do with board "DE0-Nano" which is used as reference in the book.

This approach works fine (tested by myself under Linux so far) but treats Vidor 4000 just as any other FPGA board. A more sophisticated approach would utilize the ATSAMD21 microcontroller and its connection to the FPGA.

The 2nd edition of my book will be published in spring 2019 and will contain new stuff, also about Vidor 4000 - stay tuned.

Hope this helps.
Regards,
Cord

DarioPennisi

Thank you for your help Core, it's an honour to have you here!
Let me add that without going through schematics you can start from the template project you can find here: https://github.com/vidor-libraries/VidorBitstream/tree/release/projects/MKRVIDOR4000_template_bare

This contains all the constraints and pin assignments that correspond directly to the mkr pin numbering... Top level is in verilog but you can instance a vhdl in it if you prefer that lingo.

I also suggest to give a look around on the readmes as those contain some valuable information on how to automate compilation and create images that can be downloaded via the ide.

justchris

@cord_elias
Thank's for your detailed description. I'm sure it will help other users to get into VHDL/Verilog with this board. I've send my board back to amazon und will make my first steps into FPGA on an ep2c5t144 with a USB-Blaster.

Thank's folks for your help here.

jcastillo4

Hello,

You can find some info in this page:

https://vhdl.es

Or maybe you should check for any Udemy course. There are a lot good ones.


riscvdev

#11
Jan 08, 2019, 08:29 am Last Edit: Jan 08, 2019, 08:34 am by riscvdev
Here a simple led blinking example in vhdl

i've uploaded with USBBLASTER SAM emulator

a led with a resistor must be connected between output 6 to 14 and gnd

--------------------


library ieee;


use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;



entity MKRVIDOR4000_top_vhdl is
port
(
--// system signals
iCLK : in std_logic ;

iRESETn :in std_logic ;
iSAM_INT: in std_logic ;
oSAM_INT  :  out std_logic ;

--// SDRAM
oSDRAM_CLK   :  out std_logic ;
oSDRAM_ADDR  :  out std_logic_vector (11 downto 0 );
oSDRAM_BA    :  out  std_logic_vector (1 downto 0 );
oSDRAM_CASn  :  out std_logic ;
oSDRAM_CKE   :  out std_logic ;
oSDRAM_CSn   :  out std_logic ;
bSDRAM_DQ    :  inout   std_logic_vector (15 downto 0 );
oSDRAM_DQM   :  out  std_logic_vector (1 downto 0 );
oSDRAM_RASn  :  out std_logic ;
oSDRAM_WEn   :  out std_logic ;

--// SAM D21 PINS
bMKR_AREF    :  inout  std_logic ;
bMKR_A       :  inout  std_logic_vector (6 downto 0 );
bMKR_D     :  inout  std_logic_vector (14 downto 0 );

--// Mini PCIe
bPEX_RST     :  inout std_logic ;
bPEX_PIN6    :  inout std_logic ;
bPEX_PIN8    :  inout std_logic ;
bPEX_PIN10   :  inout std_logic ;
iPEX_PIN11   :  in std_logic ;
bPEX_PIN12   :  inout std_logic ;
iPEX_PIN13   :  in std_logic ;
bPEX_PIN14   :  inout std_logic ;
bPEX_PIN16   :  inout std_logic ;
bPEX_PIN20   :  inout std_logic ;
iPEX_PIN23   :  in std_logic ;
iPEX_PIN25   :  in std_logic ;
bPEX_PIN28   :  inout std_logic ;
bPEX_PIN30   :  inout std_logic ;
iPEX_PIN31   :  in std_logic ;
bPEX_PIN32   :  inout std_logic ;
iPEX_PIN33   :  in std_logic ;
bPEX_PIN42   :  inout std_logic ;
bPEX_PIN44   :  inout std_logic ;
bPEX_PIN45   :  inout std_logic ;
bPEX_PIN46   :  inout std_logic ;
bPEX_PIN47   :  inout std_logic ;
bPEX_PIN48   :  inout std_logic ;
bPEX_PIN49   :  inout std_logic ;
bPEX_PIN51   :  inout std_logic ;

--// NINA interface
bWM_PIO1   :  inout std_logic ;
bWM_PIO2   :  inout std_logic ;
bWM_PIO3   :  inout std_logic ;
bWM_PIO4   :  inout std_logic ;
bWM_PIO5   :  inout std_logic ;
bWM_PIO7   :  inout std_logic ;
bWM_PIO8   :  inout std_logic ;
bWM_PIO18  :  inout std_logic ;
bWM_PIO20  :  inout std_logic ;
bWM_PIO21  :  inout std_logic ;
bWM_PIO27  :  inout std_logic ;
bWM_PIO28   :  inout std_logic ;
bWM_PIO29   :  inout std_logic ;
bWM_PIO31   :  inout std_logic ;
iWM_PIO32   :  in std_logic ;
bWM_PIO34   :  inout std_logic ;
bWM_PIO35   :  inout std_logic ;
bWM_PIO36   :  inout std_logic ;
iWM_TX   :  in std_logic ;
oWM_RX   :  inout  std_logic ;
oWM_RESET   :  inout std_logic ;

--// HDMI output
oHDMI_TX    :  out  std_logic_vector (2 downto 0 );
oHDMI_CLK   :  out std_logic ;

bHDMI_SDA   :  inout std_logic ;
bHDMI_SCL   :  inout std_logic ;

iHDMI_HPD   :  in std_logic ;

--// MIPI input
iMIPI_D   :  in  std_logic_vector (1 downto 0 );
iMIPI_CLK   :  in std_logic ;
bMIPI_SDA   :  inout std_logic ;
bMIPI_SCL   :  inout std_logic ;
bMIPI_GP   :  inout  std_logic_vector (1 downto 0 );

--// Q-SPI Flash interface
oFLASH_SCK   :  out std_logic ;
oFLASH_CS   :  out std_logic ;
oFLASH_MOSI   :  inout std_logic ;
iFLASH_MISO   :  inout std_logic ;
oFLASH_HOLD   :  inout std_logic ;
oFLASH_WP   :  inout std_logic

);
end MKRVIDOR4000_top_vhdl ;

architecture behavior of MKRVIDOR4000_top_vhdl is


COMPONENT SYSTEM_PLL
PORT
(
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC;
c0 : OUT STD_LOGIC;
c1 : OUT STD_LOGIC;
c2 : OUT STD_LOGIC;
c3 : OUT STD_LOGIC;
c4 : OUT STD_LOGIC;
locked : OUT STD_LOGIC
);
END COMPONENT;





--// signal declaration

signal wOSC_CLK : std_logic ;

signal wCLK8 :  std_logic ;
signal wCLK24 : std_logic ;
signal wCLK64 :  std_logic ;
signal wCLK120  :  std_logic ;

signal wJTAG_ADDRESS :  std_logic_vector (31 downto 0 );
signal wJTAG_READ_DATA :  std_logic_vector (31 downto 0 );
signal wJTAG_WRITE_DATA :  std_logic_vector (31 downto 0 );
signal wDPRAM_READ_DATA : std_logic_vector (31 downto 0 );


signal wJTAG_READ :  std_logic ;
signal wJTAG_WRITE :  std_logic  ;
signal wJTAG_WAIT_REQUEST :  std_logic ;
signal wJTAG_READ_DATAVALID :  std_logic ;
signal wJTAG_BURST_COUNT : std_logic_vector (4 downto 0 );
signal wDPRAM_CS :  std_logic ;

signal wDVI_RED  : std_logic_vector (7 downto 0 );
signal wDVI_GRN :std_logic_vector (7 downto 0 );
signal wDVI_BLU : std_logic_vector (7 downto 0 );

signal wDVI_HS :  std_logic ;
signal wDVI_VS :  std_logic ;
signal wDVI_DE :  std_logic ;

signal wVID_CLK :  std_logic  ;
signal wVID_CLKx5 :  std_logic ;
signal wMEM_CLK :  std_logic ;


component OSC_VHDL is
port (
oscena : in  std_logic := 'X'; -- oscena
clkout : out std_logic         -- clk
);
end component OSC_VHDL;



signal count : std_logic_vector (31 downto 0 );

begin

-- bMKR_D ( 6 ) <= '1'  ;

u0 : component OSC_VHDL
port map (
oscena => '1', -- oscena.oscena
clkout => wOSC_CLK  -- clkout.clk
);



process (wCLK120) begin
if (rising_edge(wCLK120)) then
count <= count + 1;
end if;
end process;

bMKR_D ( 6 ) <= count(23)   ;
bMKR_D ( 7 ) <= count(24)   ;
bMKR_D ( 8 ) <= count(25)   ;
bMKR_D ( 9 ) <= count(26)   ;
bMKR_D ( 10 ) <= count(27)   ;
bMKR_D ( 11 ) <= count(28)   ;
bMKR_D ( 12 ) <= count(29)   ;
bMKR_D ( 13 ) <= count(30)   ;
bMKR_D ( 14 ) <= count(31)   ;

wCLK8 <= iCLK ;
-- // system PLL
u1 : component SYSTEM_PLL port map
(
areset => '0' ,
inclk0 => wCLK8,
c0 => wCLK24,
c1 => wCLK120,
c2 => wMEM_CLK,
c3 => oSDRAM_CLK,
c4 => open,
 
locked=> open );

end behavior;


i've started from pwm example on a site in french


Go Up