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Topic: Where can I get the information of pin layout of GPIOs in FPGA? (Read 1 time) previous topic - next topic

javakys

Hello,

I'm testing Vidor 4000 with Arduino's sample code, "VidorTestSketch.ino", and I succeeded to make it run as what I expected.
I changed SerialFPGA1 to SerialFPGA4 and checked that the string in SerialFPGA4.println("...") is output from D1 pin as it is configured in VidorUART.cpp.

That example shows that FPGA pin 33 is connected to A0 on MKR header pin and it must be connected as that.

But I couldn't find the information of pin connection between FPGA GPIO pins and MKR header pin or minPCIE slot, anywhere.
I want to read the state of one of FPGA GPIOs thru A1 or A2.
But there is no information about which FPGA GPIO pin is connected to A1 or A2.
And how many GPIOs are configured in FPGA with VidorPeripheral library?

Where can I get that information?

Please anybody tell me about it.

Thank you.

javakys.

DarioPennisi

Hi,
Fpga pinout can be derived from schematic or from constraints file here: https://github.com/vidor-libraries/VidorBitstream/blob/release/constraints/MKRVIDOR4000/vidor_s_pins.qsf
Pin assignment for libraries should have been published but is for some reason still a company secret... Anyway, since it's Christmas.. please have a look here: https://docs.google.com/spreadsheets/d/1oAL1Iz39eCHi0IVyMiTRyekmzJg5TgeyO5t0fN6Vl4U/edit?usp=drivesdk

Happy hacking!

javakys

Hello Dalio,

Thank you for your quick reply.
I've enjoyed the webinar which you introduced Vidor 4000 at and it was so helpful for me to understand the mechanism of Vidor 4000.

Back to the topic, I can't find what I need from both documents you mentioned above.
The example, 'VidorTestSketch.ino', sets Pin number 33 as OUTPUT and makes it HIGH or LOW.
And I can get the current value of it by reading A0 on SAMD.
It shows that Pin number 33 in FPGA is connected to A0 on SAMD.

Quote
FPGA.pinMode(33, OUTPUT);
  FPGA.digitalWrite(33, HIGH);

  // The same pin can be read by the SAMD processor :)
  pinMode(A0, INPUT);
  Serial.print("Pin A0 is ");
  Serial.println(digitalRead(A0) == LOW ? "LOW" : "HIGH");

  FPGA.digitalWrite(33, LOW);
  Serial.print("Pin A0 is ");
  Serial.println(digitalRead(A0) == LOW ? "LOW" : "HIGH");
But I can't find where this configuration is defined.
Are there any additional pins which are connected to GPIO pins on FPGA?
And is there any separate numbering rule between FPGA and SAMD?
For SAMD, 0 ~ 14 looks like D0 ~ D14.
For FPGA, is 0 'D0' or does it indicate to a different one?
Can you tell me the numbering rule for GPIO pins on FPGA and/or SAMD?

Thank you.

I wish you a merry christmas!

James YS Kim

rafdev

Hi,
Fpga pinout can be derived from schematic or from constraints file here: https://github.com/vidor-libraries/VidorBitstream/blob/release/constraints/MKRVIDOR4000/vidor_s_pins.qsf
Pin assignment for libraries should have been published but is for some reason still a company secret... Anyway, since it's Christmas.. please have a look here: https://docs.google.com/spreadsheets/d/1oAL1Iz39eCHi0IVyMiTRyekmzJg5TgeyO5t0fN6Vl4U/edit?usp=drivesdk

Happy hacking!
Sorry but I don't get why the FPGA pinout and basic documentation is missing.
The spreadsheet is not helping me to understand how can I avoid the FPGA interferring on certain pins (such as A1, A2, A3) and just use that from the SAMD processor.
I guess everybody need:
1. a comprehensible map of FPGA and SAMD pin connections
2. a reference of the FPGA to understand how to enable/disable the ports
3. more FPGA examples about the obvious limitations in comparison to a micro.

javakys

Hello Dalio,

rafdev and I asked some information of MKR VIDOR 4000 but there is no update yet.

Can you let me know when you can release those information we asked?

If you will not release those information, I want to hear even such your plan.

Thank you.

BR,

James YS Kim

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