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Topic: NIOS II with 8MB external memory ( Vidor 4000) (Read 1 time) previous topic - next topic


I've successful run and debuged  a simple c code on a nios ii implemented into vidor 4000's  cyclone 10
using on chip ram ( 120 mhz ) with vidor jtag emulator .

How can i use sdram controller to use the external ram chip with a nios cpu ?

The attached  picture shows my qsys setup for sdram and nios


Dec 31, 2018, 12:32 am Last Edit: Dec 31, 2018, 12:32 am by DarioPennisi
Your setup seems fine and SDRAM should already be visible from nios. If you have trouble with that likely your parametrization of the sdram controller is not ok. Please start from the qsys we provide with graphics project on GitHub.
Also I suggest you start with 100mhz as you may have trouble closing timings at higher speeds...


If you don't have Quastus license then I recommend to use ARM with JTAG-AvalonMM bridge to FPGA.
That Nios II e is pretty slow and without hardware mult/div.

Nios II f without license will create timelimited bitfile. I think if you use arm as usb blaster and it's connected to computer then it's fine. 1h timer starts after it lost connection to quartus programmer software. Using commandline tool you can also establish serial connection to Nios II and 1h timer should starts after serial connection is closed.


Thank you very much for your answer .
i have not been able to make it work even with a 24 mhz or 100 mhz clock signal .

I've tried to build the project from github vidor repository , but some components seem to be missing in altera quartus lite (nina uart and qspi ) .

the suggested qsys (graphics ) has the sdram controller is connected to a sdram arbitrer instead of cpu and,if i'm not wrong, only data bus is connected .


I guess you didn't follow the readme on GitHub which instructs on how to patch quartus so that you have the missing blocks. In any case if you're using quartus lite you should use the lite version of the qsys which also uses nios e which is free whereas nios f is not.
Regarding connections you can remove arbiter and connect directly nios to sdram. The reason for the arbiter is that it removes some over listed fabric from qsys and at the same time provides some prioritization to allow video small to have higher precedence than could but if you're not using video you don't need it.


i 've got this message, after quartus 18.1 lite patching and build_all.sh in  pakman folder

Error (20004): Your design targets the device family "Cyclone V". The specified family is not a valid device family, is not installed, or is not supported in this version of the Quartus Prime software. If you restored a project from an archived version, your project was successfully restored, but you still must specify or install a supported device family.
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 0 warnings


Jan 02, 2019, 09:46 pm Last Edit: Jan 02, 2019, 10:55 pm by Limba
I usually used GUI for compiling. One thing that I noticed that there wasn't any lite version in project folder.

if project don't contain _lite version then this will create new project (_lite_lite) with Cyclone V family
quartus_sh --flow compile build/$PROJECT_NAME$LITE

Edit 2:
Noticed that nios shell cp command uses different permissions and it will cause problems. after commenting out cp xxx and manually copying project folder to build it started compiling design

Edit 3:
In some "_lite_sys.qsys" files have uart blocks that will cause qsys build to fail.
I have 13.12.2018 "VidorBitstream-release.zip" from github


Confirmed  edit 2 and 3

the build folder created by the script cannot be deleted from explorer

even with the patch the uart seems missing with quartus lite  (not the qspi component )

so must i rename the project folder to project_lite not to get the cyclone V error ?


Jan 03, 2019, 10:51 am Last Edit: Jan 03, 2019, 11:30 am by Limba
You can just copy paste files .qpf and .qsf and add "_lite" in the end of filename.
qpf is project file and qsf is settings file for that project.

Add this line to _lite.qsf
set_global_assignment -name VERILOG_MACRO "FREE_VERSION=1"

Edit 2:
If there are also qsys file in project then you have to add "_lite" for QIP file. Example from mbox template
set_global_assignment -name QIP_FILE ../build/MKRVIDOR4000_template_mbox_lite_sys/synthesis/MKRVIDOR4000_template_mbox_lite_sys.qip


Hi guys,
We recently fixed a couple of issues with the lite projects so you should pull the latest changes to fix these.
Regarding Pacman you will see that it's not published yet... There's only the project but it will fail compilation as we can't publish the IP blocks (yet).

If you have the lite version of quartus you should only compile lite projects. This is done automatically if you follow our guide and use command line tools whereas in quartus ide you have to manually select the right project files.


Thank you very much for your update.
I confirm that i have been able to build the project MKRVIDOR4000_graphics with the updated
github repository .

i've some questions i hope someone can answer

the qsys generated has no uart ( why ? )

I've uploaded the bitstream to the fpga with Sam USBblaster emulator,
but now how must i configure,build and run  a project into Nios II eclipse ?

In MKRVIDOR4000_graphics\build\software there are two BSP and two project


how can i import them in eclipse to create custom project ?  which must i use ?

When i create a new NIOS II application and Bsp in eclipse, selecting  "Hello world small" and

"\MKRVIDOR4000_graphics\build\MKRVIDOR4000_graphics_lite_sys.sopcinfo" the build fails with an error on
a config.h file  related to enc.c driver

the memory setup of generated BSP is totally different from demo bsp

.entry reset
.exception onchip_memory_2_0
.text onchip_memory_2_0



.text qspi_avl_mem
.rodata qspi_avl_mem
.rwdata onchip_memory2_0
.bss onchip_memory2_0
.heap onchip_memory2_0
.stack onchip_memory2_0
.entry qspi_avl_mem
.startup startup

with these offset

onchip_memory2_0 0x00A00020 - 0x00A03FFF 16352 onchip_memory2_0 32
reset 0x00A00000 - 0x00A0001F 32 onchip_memory2_0 0
qspi_avl_mem 0x008E0004 - 0x009FFFFF 1179644 qspi_avl_mem 917508
startup 0x008E0000 - 0x008E0003 4 qspi_avl_mem 917504
reserved 0x00800000 - 0x008DFFFF 917504 qspi_avl_mem 0
SDRAM_ARBITER 0x00000000 - 0x007FFFFF 8388608 SDRAM_ARBITER 0


it's not clear to me why startup has 917504  offset

i'm sorry but a lot of things seems missing into documentation
for example there is a schematic but no BOM and no pin output layout and connection

for example a pinout diagram like that at this link  



Success !!

using MKRVIDOR4000_graphics_lite SYS as example

NIOS + uart + sdram and software running in sdram both for instruction and data


The reason lite projects lack uart is that we used the 16550 compatible uart up which is not included in the free version of quartus so we had to remove it for the lite builds.

Importing in eclipse is a bit more complex as you have to import them as external makefile projects. Unfortunately this won't allow full functionality as the whole eclipse thing from Intel is a bit flawed.
The reason why things are different when you create your nap is simply because our settings are customized but you can get the same settings if you copy the settings.bsp file from our to your directory

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