Go Down

Topic: A clear and simple flow (Read 24179 times) previous topic - next topic


Thanks, now the download doesn't hang anymore.

The Philippe's led blink example works each time I upload it but if I recompile it under my Quartus 18.1
replacing the old app.h with the new app.h (app.ttf), I don't see the signal on D6.

Philippe, what is missing?


Just to be sure : Have you bit reverse the stream generated by quartus ?

You have to execute java ReverseByte MKRVIDOR4000.ttf app.h

where :
- MKRVIDOR4000.ttf is the quartus output file (or anything.ttf)
- app.h will be the generated file to include in the sketch

Java executable ReverseByte is available here :



Just to be sure : Have you bit reverse the stream generated by quartus ?

No, I didn't know, only right now I see your site

before I was directed on

Reversing the byte it works.

Question: is this step mandatory for ANY project or your project has something special?

Tomorrow I'll have to try with my 7-bit counter project from VidorBitstream-release//BareMinimum.

Thanks a lot for your help, at the end I have to write a little user manual for my colleagues.


Sorry, my bad, I thought I had linked the google translate of the guide, not the download page ><.
Reversing is needed for everything you build, also using the "official" scripts, there it is done with a go-program instead of the java one :P.


Well, it seems that if I use the Philippe's project as starting point all works and I'm very satisfied!

Thanks to everyone!

The internal oscillator freq is 66.66 MHz (more or less, measured with a 100 MHz Rigol oscilloscope).
Th external signal iCLK as FPGA input freq is 48 MHz.

Now I'm going to write my experience to be duplicated by colleagues and students.

If I'll have some difficulties I'll post again.

My case at Intel regarding Modelsim simulation is


could be interesting.

Thanks again


Hi guys,
Sorry to jump in late. Looks like we still need to clarify documentation but in the meantime thank you for your patience and enthusiasm.

The infrastructure we put together assumes you will use JTAG bridge and softcore to communicate with arm. This is why the Arduino stuff in the arm side stops working when you start from the bare project which doesn't have the above.

The issue we didn't document well is that template bare does not produce a library to be loaded via ide because you would not be able to communicate. This is for sure my fault and I apologise for this. Also, note that if you manage to load the fpga bitstream it would work only after you call fpga.begin as that enables clock output from samd, which is used by the ppl that generates all the clocks in the fpga. In the next days I'll try to update stuff so that things get a bit easier...


Also there should be documents how to use direct jtag-avalonmm for memory access. In this case we use quartus jic for programming fpga config flash.

Only unknown part is how to start SAMD21 side communication for jtag and enable FPGA clock without FPGA library or with USB Blaster lib.

Other issue may be to use JTAG AvalonMM with active signaltap. Workaround would be to use SPI/uart for communication to FPGA?
Uart to Avalon MM should be pretty easy solution.


Hi Limba,
tomorrow morning you'll see updates in the readme of the git repo which will contain much more info on how projects are working and how to correctly generate an arduino library out of the toolchain.
regarding your questions...
1) we're not using Intel's JTAG to avalon MM bridge because it has too much overhead. our bridge source code is in the ip dir in github and if you just want to use that without softcore then you can simply use the writeBuffer and readBuffer methods of VidorJTAG object (defined here: https://github.com/vidor-libraries/VidorBitstream/blob/release/ip/RPC/arduino/VidorUtils/src/VidorJTAG.cpp) and used for example here: (https://github.com/vidor-libraries/VidorBitstream/blob/e098c778ef6aaaec204a66dfb3e1bebdc395ca13/ip/RPC/arduino/VidorUtils/src/VidorMailbox.cpp#L40)
unfortunately at the moment these files are in the RPC ip which is not that correct (VidorJTAG should be under the JTAG Bridge IP) but it's clean up work in progress...
2) enabling FPGA clock from SAMD side is done calling enableFpgaClock function, defined in the core here: https://github.com/arduino/ArduinoCore-samd/blob/67bf93e52e52ccb75142bbbeb6588ecf9b042952/variants/mkrvidor4000/variant.cpp#L221
3) we're working on having JTAG bridge running in parallel with signaltap and other functions. unfortunately there's some Intel magic we are trying to demistify...

hope this helps


Jan 29, 2019, 03:34 pm Last Edit: Jan 29, 2019, 03:43 pm by tcmichals
>3) we're working on having JTAG bridge running in parallel with signaltap and other functions. unfortunately there's some Intel magic we are trying to demistify...

Can you please provide more information on this issue?  (I'm also trying to understand how to use signaltap with jtag etc)

From JTAG_BRIDGE.v, the code still uses the megafunction VJTAG_INST from Intel?   

Also, the NIOS processor does not process the request, it just pushes the request onto the Avalon bus? 

(Thank you)


From JTAG_BRIDGE.v, the code still uses the megafunction VJTAG_INST from Intel?   

I think main problem with this is in SAMD side. Now they have to provide binary library of USB Blaster (because of licensing) and that won't allow jtag commands from sketch. So for memory access you need to use other serial connection.


the issue with having Quartus/Eclipse functions work in parallel to SAMD is simply that USB Blaster just receives "raw" JTAG signal states so on the SAMD side we should know where to interrupt the stream without breaking what's being transmitted from the other side... right now this is still somehow not always well defined, hence having the two working reliably in parallel is not yet doable


After project design in Quartus and simulation with Modelsim, last step:
the sketch.

On the Philippe's tutorial I see the JTAG pins mapped on pins 12,13,14,15:

#define TDI 12
#define TDO 15
#define TCK 13
#define TMS 14

--> I suppose the pin named TDI is mapped on physical pin 12 of the processor, right?

If yes, looking at MKRVidor400 schematic, I see the pins 12,13,14,15 are not for JTAG purpose.
I'd like to use the processor pin 12 (pin A6 on the shield connector) and 13, 14, 15 for my project.

1- is the above JTAG a mapping error?
2- (I'm new to Arduino) is the 12 on the above #define the processor physical pin number?




What I checked from schematics JTAG is in PA12-PA15 (pins 21-24). JTAG is only between ARM and FPGA. There are place for 10 pin connector or cable buttom side of pcb.

JTAG connection library is in Users\<User_Name>\Documents\Arduino\libraries\VidorPeripherals\src\utility and jtag_host.cpp file

So defined numbers are PA io numbers.


Thanks Limba.

Do you know if the JTAG pins #define on Philippe's sketch are needed in order to make
the boot to work? (Can I comment them?)

If they are needed, why the pins are different from schematics one and how they can
work there?


Waiting for a reply from Philippe,

his example inlcudes a local (with .ino file) jtag.h.
Opening the .ino, the IDE opens also app.h, jtag.h and jtag.c (this is local as jtag.h).
I cannot find any #include of jtag.c, but it is needed because there are calls to its routines.

So, I try to:

1- comment   //#include "jtag.h"
  --> jtagInit()  not found

2- replace   #include "jtag.h" --> #include <jtag_host.h>  which is in the place you indicated
   --> jtag_host.c  file not found

How to include the path Users\<User_Name>\Documents\Arduino\libraries in the sercah path
for compilation?

Where the search paths are defined?

Thanks for the help.

Go Up