So we need to wake up in sync with the middle - to make sure its not too early nor too late - of the square pulse at the collector's and then wake up, say every millisec five times to make sure we have the 'real mains' and not synced parasit. The location of the mid of the pulse - assuming 50% duty cycle - can be found by sampling the wave say every milli to find five 'lows' followed by five 'highs' and adding 2.5ms to the previously found transition. Now we are well centered and if all - or most, say 3 out of 5 are high and that this occurs for 100 ms (5 mains cyclec) then we decide 'switch closed'. Conversely, if centered, by a 20ms translation of above center we find mostly 'lows' then we decide that the switch is open. While the switch is closed, We will need to redo the centering every now and then to compensate for the drift of cpu's clock relative to the 50 Hz and do the all thing for every switch. I said wake up because obviously, it must be done in interrupts. This may work but, then, why not going the orthodox way with a DSP and replace the unfortunate capacitor by an FIR low pass? Say with constant coefficients all ones and one bit ADC? Could be implemented as circular buffer where samples are inserted at the head pointer and extracted from the tail=head+1 (modulo) and FIR output = sum + *head -*tail is compared to a threshold [edit: with hysteresis] and the results is the switch state?