H-Bridge protection?

this is my first h bridge so please be gentle
lets say D1 and D2 are arduino digital pins, would this fry the chip? any tips?
do i need an optocoupler?

Shoot-through current spikes will be large as both high-side and low-side devices are on simultaneously for a few microseconds or more on every transistion.

You need to switch diagonally opposite devices together, not same-side devices together. You need to allow dead-time between switching one path off and the opposite path on.

You can have separate drive to all 4 devices and arrange the software to provide deadtime. This is more flexible too.

Two of your MOSFET symbols are upside down.

MarkT:
Shoot-through current spikes will be large as both high-side and low-side devices are on simultaneously for a few microseconds or more on every transistion.

You need to switch diagonally opposite devices together, not same-side devices together. You need to allow dead-time between switching one path off and the opposite path on.

You can have separate drive to all 4 devices and arrange the software to provide deadtime. This is more flexible too.

Two of your MOSFET symbols are upside down.

oh i see! stupid mistake my bad


(I've no idea how to mirror icons on this software)

The problem with shoot-through is due to the extremely low on-resistances of power MOSFETs and the substantial time it takes to charge/discharge the gate capacitance with a weak drive (1k resistor here).
12 volts across two 40 milliohm MOSFETs pulls 150A if its available. Typical symptoms are the 12V rail
decoupling capacitors and the MOSFETs getting very hot and lots more power drain than you expected.

However if you are not doing any PWM the transient spikes only happen on reversing/starting/stopping,
which won't be as disastrous.

MarkT:
The problem with shoot-through is due to the extremely low on-resistances of power MOSFETs and the substantial time it takes to charge/discharge the gate capacitance with a weak drive (1k resistor here).
12 volts across two 40 milliohm MOSFETs pulls 150A if its available. Typical symptoms are the 12V rail
decoupling capacitors and the MOSFETs getting very hot and lots more power drain than you expected.

However if you are not doing any PWM the transient spikes only happen on reversing/starting/stopping,
which won't be as disastrous.

i am planning to PWM yes.
should i reduce the value of R1 & R2?
also, do the diodes not prevent the shoot-through? or what am i missing
thank you very much for all the help.

Gate drive is wrong.
You need to find a diagram that drives the bottom-left fet and the top-right fet with one NPN transistor, and the bottom-right and top-left with another NPN transistor.
Only then will you be able to code some dead-time between switching.
Leo..

Shoot-through happens when Q3 turns ON before Q1 has time to fully turn OFF, you need a small "dead time" between switches. Also D1 - D4 are redundant, notice they are in parallel with the MOSFET body diodes which do the same thing. But, of course, they won't hurt.

Actually using schottky diodes to parallel the body diodes is a common thing to do to reduce losses. But without any deadtime they are indeed redundant!

thanks a lot for all the information :slight_smile: , its being very helpful for a newbie like me.

Wawa:
Gate drive is wrong.
You need to find a diagram that drives the bottom-left fet and the top-right fet with one NPN transistor, and the bottom-right and top-left with another NPN transistor.
Only then will you be able to code some dead-time between switching.
Leo..

did i get this right?

No, because the gate of Q4 has to go HIGH when the gate of Q1 goes LOW.

Could try the drive transistor between the gates of Q1 and Q4.
Q5 emitter to gate Q1, Q5 collector to gate Q4.
220ohm resistor from Q5 emitter to ground, 390ohm resistor from collector Q5 to 12volt.
Usual 1k base resistor.
Same for the other side (Q6).
This will only work if the N-channel fets are logic level (not the IRF640).

Maybe better to use a dedicated gate driver chip, with buildin protections.
Designing a mosfet H-bridge is not a beginner's job.
Leo..

Its easier to build H-bridges using the chips purpose-designed for the job of course - one chip can drive all 4 MOSFETs of an H-bridge, enforce deadtime, provide bootstrapped gate drive, detect under voltage, etc etc.

MarkT:
Its easier to build H-bridges using the chips purpose-designed for the job of course - one chip can drive all 4 MOSFETs of an H-bridge, enforce deadtime, provide bootstrapped gate drive, detect under voltage, etc etc.

i did some research and found out what you mean exactly, thanks for the heads up
do you have any recommendations for a P and N channel logic level mosfet that is fairly common(So its easier to find)

Wawa:
No, because the gate of Q4 has to go HIGH when the gate of Q1 goes LOW.

Could try the drive transistor between the gates of Q1 and Q4.
Q5 emitter to gate Q1, Q5 collector to gate Q4.
220ohm resistor from Q5 emitter to ground, 390ohm resistor from collector Q5 to 12volt.
Usual 1k base resistor.
Same for the other side (Q6).
This will only work if the N-channel fets are logic level (not the IRF640).

Maybe better to use a dedicated gate driver chip, with buildin protections.
Designing a mosfet H-bridge is not a beginner's job.
Leo..

No need for a logic level P-channel fet if you use my recommended resistor value.
This one and this one seem easy to get.
I do agree with MarkT. Use a dedicated driver chip, and the recommended mosfets for that.
Leo..