Thanks MartinL for your reply!
When I implement this configuration you mentioned in my code, the time goes from 500us to 330us, which is very good, but still cant get 250us.
ADC->CTRLA.bit.ENABLE = 0; // Disable the ADC
while(ADC->STATUS.bit.SYNCBUSY); // Wait for synchronization
ADC->SAMPCTRL.reg = 0x00; // Reduce the sample time by (63 + 1) * (512 / 48MHz) / 2
ADC->CTRLA.bit.ENABLE = 1; // Enable the ADC
while(ADC->STATUS.bit.SYNCBUSY); // Wait for synchronization
Is there something I missed? Or another configuration I should consider?