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Topic: VGA output: PLL used for clock has jitter (Read 5152 times) previous topic - next topic

Limba

From schematics M0-2 (101) -> Fast Active Serial
Chapter 6 from userguide
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf


CONF_DONE goes HI after configuration is done and INIT_DONE go HI after FPGA enters user mode and all IO:s change weak pullup to application specific.

One thing came to my mind.
So if boot image provided by arduino have clock unused it maybe driving GND. So before loading your image it may be problem to give clock to that pin. It may be better to use your own pin as "user conf_done" that is pulled HI after your image is loaded. Note all pins have weak pullup when FPGA is not configured.


famo

I've not specified before, but the scope obervations I've made are with
the orginal connection between the CPU SAM_PORTS.GCLK and R3,
so I've observed the board during its normal boot.
My hope was to identify the CONF_DONE node but without success.

Here the 10k resistors I've found:

purisame

Haven't had any issues with high-speed clocks on HDMI, but that might just be because it's digital TX.

Did you try measuring the jitter of the external oscillator used by SAMD21: ABS07-32.768KHZ-9-T ?
There could be noise coming from the power supply itself.

famo

No, I didn't, when I will have time I'll do it.

Looking at the SAMD21 datasheet, the DFLL48M internal 48 MHz generator from the
external 32.768kHz oscillator reference (attached) ha a couple of interesting parameters

Symbol    Parameter                         Conditions         Min. Typ. Max. Units
fOUT      Average Output frequency fREF = 32.768kHz    47   48   49    MHz
Jitter      Cycle to Cycle jitter         fREF = 32.768kHz     -     -   0.42  ns

What I could think is that the DFLL48M output frequency changes in time
but the cycle-to-cycle jitter is 0.42 ns.
The word "average" is a bit obscure: what are the minimum and the maximum values?
Could I have, during the VGA raw scan, a pixel frequency variation so big to see
on the screen a corresponding pixel jitter?
Here my answer is yes.
The 48 MHZ clock jitter is easily visible with an oscilloscope triggering on it
and going to see what happens on the clock cycles more and more far away the
triggering one.
Please try.


Limba

#19
Jul 06, 2020, 11:47 am Last Edit: Jul 06, 2020, 11:55 am by Limba
Another idea come to my mind.
How to use other clock in and separated enable from FPGA. In your design you set that pin HI from PEX_PIN33 (B9 in FPGA) as enable and PEX_PIN31 (A9 in FPGA for clock in to PLL) for clock in.

famo

I've made a similar attempt with iMIPI_CLK input.
It is LVDS and I've used a resistive network to set the common level for the differential inputs and
assure a good voltage swing, but no hope to receive a clock from this pin.

OK, I'll try with PEX_PIN33 pin and I'll inform you on results,
thanks again.

Limba

remember to configure pin right. I think PEX pins are 3v3 LVTTL.

famo

Yes, already checked for that, it is as you say.

famo

Success!

I've instantiated another PLL to avoid to switch between clocks.
I've used a PCIe breakout board project found on the web,
submitted myself to JLCPCB and mounted in my lab.
You can see the oscillator indicated by an arrow mounted in a "dead bug" way.

The display is very sharp (my photos are worse).
You can see a counter running.

To perform the final check I should see if the on-board 32.768 kHz
oscillator is itsef jittering.
I'll inform you about.

Thanks everybody for help.


Limba

Do you have partnumber of that mini PCIe connector?
How fast was JLCPCB delivery?

famo

Digi-Key 2041119-1.

JLCPCB with DHL-express takes a  few days (less than 1 week).


32.768 kHz oscillator jitter: none visible on my scope.

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