Looking at the datasheet, it appears all of the available I/O pins are multiplexed to at least one TCCx Timer. Does this indicate that each pin is capable of producing a PWM output (depending on the device configuration)?
Note that they can't all run PWM at the same time. because some of the timer outputs are "optionally connected" to multiple pins, and some of the outputs are merely complements of some other timer output (as Martin said, in slightly different words...)
Hi gabenix,Wow, there's nothing rough about your draft image, Microchip/Atmel should use it in their datasheets. It gives a nice overview of each pin's capabilities.In the SAMD21 datasheet, section 2 named "Configuration Summary", it details each variant's on-chip peripherals. The datasheet could make this much clearer, especially since they've now added a whole new group of optimised variants: SAMD21ExxA, SAMD21ExxB, SAMD21ExxC, SAMD21ExxD and finally the SAMD21ExxL.The SAMD21E (in any of its new varieties) has only 4 SERCOM modules: SC0 through to SC3.All varieties of the SAMD21E contain TCC timers: TCC0, TCC1 and TCC2, but only the SAMD21E17D and SAMD21E17L incorporate the additional TCC3 timer.
In the SAMD21 datasheet, section 2 named "Configuration Summary", it details each variant's on-chip peripherals.
for i in range(1,32): showChipPin(str(i)) Chip Pin 1 on ATSAMD21E17L is PA02 ADC: AIN0 pmux:B DAC: VOUT pmux:B EIC: EXTINT2 pmux:A PORT: P2 pmux:default TCC3: WO0 pmux:FChip Pin 2 on ATSAMD21E17L is PA03 ADC: AIN1 pmux:B DAC: VREFP pmux:B EIC: EXTINT3 pmux:A PORT: P3 pmux:default TCC3: WO1 pmux:FChip Pin 3 on ATSAMD21E17L is PB04 AC1: AIN0 pmux:B ADC: AIN12 pmux:B EIC: EXTINT4 pmux:A PORT: P36 pmux:defaultChip Pin 4 on ATSAMD21E17L is PB05 AC1: AIN1 pmux:B ADC: AIN13 pmux:B EIC: EXTINT5 pmux:A PORT: P37 pmux:default : :Chip Pin 31 on ATSAMD21E17L is PB02 AC1: AIN2 pmux:B ADC: AIN10 pmux:B EIC: EXTINT2 pmux:A PORT: P34 pmux:default TCC3: WO2 pmux:FChip Pin 32 on ATSAMD21E17L is PB03 AC1: AIN3 pmux:B ADC: AIN11 pmux:B EIC: EXTINT3 pmux:A PORT: P35 pmux:default TCC3: WO3 pmux:F
I usually put together a spreadsheet; doing the work gives me a better understanding of how a particular chip actually works, along with limitations of the pinout. And it's useful to be able to sort based on different columns... Lately, I've been working on a python program that parses the higher-level .ATDF machine description file that is provided, translating it to various more readable formats.I wonder if it would be possible to go programmatically straight from the descriptions to some sort of image...
gabenix,Nice job. I see your reference to functions C - G. Are those functions defined somewhere in the SAMD21 Family datasheet?
7.1 Multiplexed SignalsEach pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.