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Topic: Vidor4000 Routing signals by fpga (Read 751 times) previous topic - next topic

Dueet

I'm reading more around then posting.   But i have a project now and while there is a lot of info already out there.. I was not entirely sure if the Vidor can help me out on this build.   So i rather ask first before ordering and finding out that my idea doesn't work.

The Vidor4000 has a SamD21 which i'm quite familiar with as we run a lot of projects on this processor.  But i now need some kind of router to distribute and switch around 16 to 32x  i2s ( Sound ) towards multiple outputs. 

Kind of a router functionality..   And since i2s is only 2,5 / 3,5Mhz max clock speed.  It is not a very heavy signal..  But due to the many in, Many out..  i was like well that might fix my needs..  

The Vidor ports seems very well capable handling the speed of those signals.   But got a few questions due too NO experience yet when it comes to FPGA's..

1) When i couple an input pin > to a bus >  bus to output mux > Outputmux to output pin.    Is there any processing of the signal done?  or is it really transparent at that point??
2) Would i be able to set things like this up by the Arduino Api or should i start direct building blocks in Quartus?
3) When building blocks in Quartus with control inputs to trigger certain actions inside that block,  How do you couple this to the Arduino Api to control those actions from the D21.  
4) Seems that development on the Vidor4000 is halted as the Github is not maintained for 2 years now.     Streaming Api still seams to be non existing ( While a serial driven connection could be handy in a lot of occasions )   So are there any future plans or is the project a bit dead in the water?  Just wondering what your opinions are regarding to this? 

Kind Regards,
Daniel

VStrakh

There is no 'transparency' when signal is passed through from input pin to output pin.
The data will always pass through multiple logic elements, and the exact time required to propagate depends on many factors:
- the design itself (how many logic elements are involved in selectors/multiplexers)
- the routing overheads because related logical elements aren't close enough, so some intermediate elements were wasted to behave like a wire.
- the propagation delays within the routing fabric, and the logic elements.

You can assume there is always some 'processing', but what kind of processing - asynchronously passing data through, or synchronizing the signal edges to some processing clock - that depends on the design and your needs.
In the simplest case of passing data through, as if it were relays/wires - expect delays of some nanoseconds from input pin to output pin, and expect the skew between multiple parallel lines, because typically signals will take different routes, going through physically distant logic elements. You can try to minimize the skew by constraining the design, but this would require detailed knowledge of your project needs. Perhaps it would be preferable to synchronize the signals, then the fitter would be able to lay the elements in a way that guarantees signal changes to fall within well defined time window.

I'd say you should prepare to build the required configuration yourself, so learn Quartus and a bit of Verilog/VHDL.

In my view the Vidor support looks 'dead' exactly because you can't fit every imaginable possibility within one design, and producing new configuration is a real job that takes time and efforts. And the long awaited 'web editor' that would allow inexperienced user to combine only needed pre-built blocks in one design - still not there, and is likely would be extremely hard to do, considering how much cpu time is needed to recompile a decently big design.


Dueet

Thank you for your answer. 

Well with a sample clock of max 3,5 Mhz i'm not really concerned about a few nano seconds inside the FPGA.   But it was more like am i'm able to route in to out..  

I come from C oriented programming were the SamD32 is line by line base.. And you would not be able to connect an input pin to an output pin in an AVR without running code to make sure the state changes are detected and set to the output pin..     So that was more my concern about the FPGA style setup.. 

I'm not afraid of working something out in Quartus..    There are more then enough tutorials on how to create things inside those units..     But i need to control it from the SamD21 so i need a part of that integration that they use to control the FPGA..    Which i have to dive deeper into if it is a Memory read write setup or some serial command structe to control the FPGA from the Arduino lib.  

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