There is no 'transparency' when signal is passed through from input pin to output pin.
The data will always pass through multiple logic elements, and the exact time required to propagate depends on many factors:
- the design itself (how many logic elements are involved in selectors/multiplexers)
- the routing overheads because related logical elements aren't close enough, so some intermediate elements were wasted to behave like a wire.
- the propagation delays within the routing fabric, and the logic elements.
You can assume there is always some 'processing', but what kind of processing - asynchronously passing data through, or synchronizing the signal edges to some processing clock - that depends on the design and your needs.
In the simplest case of passing data through, as if it were relays/wires - expect delays of some nanoseconds from input pin to output pin, and expect the skew between multiple parallel lines, because typically signals will take different routes, going through physically distant logic elements. You can try to minimize the skew by constraining the design, but this would require detailed knowledge of your project needs. Perhaps it would be preferable to synchronize the signals, then the fitter would be able to lay the elements in a way that guarantees signal changes to fall within well defined time window.
I'd say you should prepare to build the required configuration yourself, so learn Quartus and a bit of Verilog/VHDL.
In my view the Vidor support looks 'dead' exactly because you can't fit every imaginable possibility within one design, and producing new configuration is a real job that takes time and efforts. And the long awaited 'web editor' that would allow inexperienced user to combine only needed pre-built blocks in one design - still not there, and is likely would be extremely hard to do, considering how much cpu time is needed to recompile a decently big design.