Pre-Buy Question: Can the FPGA load a bitstream from Flash

[lenasteam]

Dear all,

before buying a copy of the MKR Vidor 4000, it would be great if those already owning one could answer me the following, so that I know that I can use it:

1. I'm still puzzled about how to get the FPGA bitstream into the FPGA. Can the FPGA load it from the attached flash memory chip? Or does it have to be uploaded from the MCU every time the board is powered up? If I get it correctly, the latter approach is followed by programs using the VidorGraphics library.
2. If the answer to (1) is yes, is there a way to program the flash using the MCU? The VidorGraphics library appears to load the FPGA bitstream from the MCU, but what about write-through to the flash memory?
3. If the answers to (1) and (2) are yes, are there example projects for uploading the flash memory content via Wifi? Since the Wifi components is an ESP32, there may be a way to program it as well?
4. Oh, and I'm confused about the fact that the FPGA bitstream size is ~500 kB if I get it correctly, but the SAM MCU only has 256 kB internal Flash size. So how does this fit?

I don't find direct answers to these questions in the documentation, so it would be great if any of you could answer some or all of those. I'm currently comparing the MKR Vidor to the Spartan Edge Accelerator board from a different manufacturer, which follows a very different approach, though: They use an ESP32 MCU with 4 MByte Flash memory and a Xilinx FPGA that has no memory directly attached. So while the MCU needs to upload the Bitstream every time the board boots up, there is plenty of space for it. Implementing a Wifi access point program for the MCU to allow uploading the FPGA bitstream was not too difficult in that case. But the FPGA has no external RAM, which is a bit limiting for some projects (especially when using HDMI output, which both boards compared have).

[VStrakh]

FPGA is loading its config from the flash chip, there is no internal flash in the Cyclone 10 LP, and there is not enough memory in the MCU.
The flash chip contains multiple images, with the first image being taken by a bootloader, implementing stuff required by MCU to request fpga restart with selected image, as well as stuff required for flash chip access. When powered up the fpga loads from the first image, and provides services to MCU to upload user-defined configuration streams into selected flash areas. MCU then issues command to fpga bootloader to reboot fpga from the new starting address in flash.
The interface is not disclosed though, and there is no direct access to the flash chip from the MCU side.
The project you build will be larger than the memory in MCU, when uploading the project the programmer will recognize section beyond the mcu flash area, and will use interface provided by fpga's bootloader image to write data into fpga configuration flash chip.

[lenasteam]

Thanks for the answer!