As the original thread is bugged, the second page is just blank ill continue posting in this thread until the old one is fixed or the problem is solved in any other way;)
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Hi all, I havent been online for some time due to the start of my study at the technical universty Eindhoven, (electrical engineering

) However i have made some progress in the meantime.
I made a clear layout for how i want to controll my matrix. for now i will have four modes:
1) 'normal' arduino visualizer mode, works like a normal matrix controlled by nested and linked shift registers (details further on)
2a) lm3914 mode; lm3914 collumwise controlled; lower 6 rows are blue and controlled by low freqs, 6 rows above that are green and controlled by middle freqs, top 4 rows are red and controlled by high freqs. Arduino controlls which rows are on or off. 'loudness' is shown from center outwards.
2b) lm3914 mode; same as above only that the loudness is shown from the sides towards the center.
3) graphic equalizer mode, arduino controlled, inputdata generated from the dual mseq7 shield.
the basic representation of how the matrix is controlled is like this:
[audio]-{3}->\#\-{3}->[mseq7 shield]-{?}->[arduino]--{10}-->[shift register module]--{64}-->/$a/[mode selector mux logic]-{64}->[matrix]
\#\-{3}->[lm3914 board]-----------------------{48}--------------------------->/$b/
were the \#\ thing is a duplication of the signal and the /$(a|b)/ things are inputs for the mux logic board. the numbers in the curled brackets show the bus-width.
it looks relatively simple until now but to get all the ideas worked out took me quite some time, and i still am not yet done with the mux logic.
(partly because i have a load of logic ic's lying around i decided to build the multiplexor-like circuit myself!)
now about the shift register module (as the rest is quite straight foward compared to it)
i have devided the matrix inputs into 4 groups, 16 row v+ inputs, 16 red collum ground 'inputs', 16 green collum ground 'inputs' and 16 blue collum ground 'inputs'.
the v+ are controlled by 2 74hc595 shiftregisters, serialdata linked through, latch and clock on each chip combined to the latch and clock of the other chip.
the columns are controlled by 2 74hc595 shiftregs aswell, same config but the outputs are connected to two uln2803 chips to make them inderectly sink the collums when turned on.
the problem is that if i want to control these 4 sets or shift registers i would need 12 pins, 4x[serial data, clock, latch] which was just not practical. so i came up with
the following solution:
i added an extra shift register which controls the clock and latch of each of the 4 pairs of shift registers. now i only need 7 datalines to control all the shift registers.
serial data, clock and latch for the 'controlling' shift register and only serial data for each of the four pairs as the clock and latch signals of those are managed by the controlling shift register.
connected in the following way:
Q0 = clock v+ regs
Q1 = latch v+ regs
Q2 = clock red regs
Q3 = latch red regs
Q4 = clock green regs
Q5 = latch green regs
Q6 = clock blue regs
Q7 = latch blue regs
I realize this isn't the smartest or fastest way but i liked the idea and want to see if i can get it to work. (if it doesnt im thinking of using a 27c256 EEPROM IC which i found a few days ago.
i've already started on coding the first mode and this is what i've got until now, it would be great if someone could look through it (when they have time left or feel like doing that) to see if
it seems sort of reasonable to work or not.
I'll keep you guys posted on further updates!!
the code:
const int ctrl_latchPin = 2, ctrl_clockPin = 3, ctrl_dataPin = 4;
const int a = 5, b = 6, c = 7, d = 8;
void setup() {
pinMode(ctrl_latchPin, OUTPUT);
pinMode(ctrl_clockPin, OUTPUT);
pinMode(ctrl_dataPin, OUTPUT);
pinMode(a, OUTPUT);
pinMode(b, OUTPUT);
pinMode(c, OUTPUT);
pinMode(d, OUTPUT);
Serial.begin(9600);
Serial.println("reset");
}
int bit_int(int bitarray[]){
int tempdata = 0;
for(int i = 0; i < 8; i++)
{
if(bitarray[i]==1)
tempdata += 1 << i;
else
tempdata = tempdata;
}
return tempdata;
}
void shiftreg(int whichReg, byte bitdata){
int data = int(bitdata), clktemp = 0;
int datarray[8] = {0};
int ctrlarray[8] = {0}; // = {clk vss, latch vss, clk red, latch red, clk green, latch green, clk blue, latch blue}
for(int i = 0; i<8; i++)
datarray[i] = bitRead(data, i); //placing data into the array, LSB will end up on place 0 of the array
for(int j = 8; j>0; j--)
{
ctrlarray[(2*whichReg)]=0; //reg clk = low
clktemp = bit_int(ctrlarray);
shiftOut(ctrl_dataPin, ctrl_clockPin, LSBFIRST, clktemp);
digitalWrite(char('a'+whichReg), datarray[j]);
ctrlarray[(2*whichReg)]=1; //reg clk = high
clktemp = bit_int(ctrlarray);
shiftOut(ctrl_dataPin, ctrl_clockPin, LSBFIRST, clktemp);
}
}
void loop() {
registerWrite(0,0,HIGH);
delay(250);
registerWrite(1,7,HIGH);
delay(250);
registerWrite(1,7,LOW);
delay(250);
registerWrite(0,0,LOW);
delay(250);
}
void registerWrite(int whichReg, int whichPin, int whichState) { //vss = 0, red = 1, green = 2, blue = 3;
unsigned int bitsToSend = 0;
int controlbits = 0, tempdata = 0;
int ctrlarray[8] = {0}; // = {clk vss, latch vss, clk red, latch red, clk green, latch green, clk blue, latch blue}
digitalWrite(ctrl_latchPin, LOW);
ctrlarray[(1+(2*whichReg))] = 0; //set data to make latchpin low
tempdata = bit_int(ctrlarray);
shiftOut(ctrl_dataPin, ctrl_clockPin, LSBFIRST, tempdata); //vss latchpin high
bitWrite(bitsToSend, whichPin, whichState);
byte registerOne = highByte(bitsToSend);
byte registerTwo = lowByte(bitsToSend);
shiftreg(whichReg, registerOne);
shiftreg(whichReg, registerTwo);
ctrlarray[(1+(2*whichReg))] = 1; //set data to make latchpin high
tempdata = bit_int(ctrlarray);
shiftOut(ctrl_dataPin, ctrl_clockPin, LSBFIRST, tempdata);
digitalWrite(ctrl_latchPin, HIGH);
}