In my (Linux )embeded device I have 4 SDRAM modules.( Each module is of
16 bit data bus and 13 bit address bus )
I need to find out how they are addressed
if it is like this :
1st address in module 1
2nd address in module 1
3rd address in module 1
4th address in module 1
5th address in module 1
6th address in module 1
7th address in module 1
8th address in module 1
...
...
the last but one address in module 4
the last address in module 4
or
1st address in module 1
2nd address in module 2
3rd address in module 3
4th address in module 4
5th address in module 1
6th address in module 2
7th address in module 3
8th address in module 4
..
..
the last but one address in module 3
the last address in module 4
Is it possible?
( Via JTAG I can "talk" to CPU directly and write to an address, if it helps)
Thanks
Yes, you are right.There are 2 more bits ( marked BA0 and BA1) marked as bank select address( each module consists 4 internal banks).
Besides there is CS( chip select) bit.
Do you think that these two(= BA0,BA1) or even those three( =BA0,BA1 and CS) bits are 14 and 15 and 16 bits that is they are the MOST significant bits( the first bits in the address) or the LEAST significant( the last 3 bits?)
Thanks for the reply
Remember that there is RAS and CAS too - the address bus is used to select a row address and a column address, so there could be anything up to 26 bits of address from the 13 bit address bus. To know how many column bits and row bits there are you need to read the data sheet for the ram modules.
I think bank selects should normally be MSBs (but I saw one design where they were LSBs)
As for interleaving, 12121212.....34343434 and 11221122....33443344 are also possibilities. Are you able to remove the modules? If so, do a memory bandwith test with 1 module installed and 2 modules installed - if it goes faster, it is interleaving memory addresses.
Oh,is it so complicated?
ALl that I want to do is testing if these 4 modules are working OK or not.So I would like to test that SDRAM modules like memory test programs do.
I first write value and then read it back.If the values are the same, the address is OK.
But if not , the address is faulty and that means also the module sis faulty( or a path to that module).
But to be able to find out which module must be changed I must know which address belongs to which module.
Do you have any idea how to find out?
if I remove any module( or disconnect a data bit ), the device will not start.Does it mean that it uses interleaving memory address?
Thanks for the reply.
Is there any algorithm how to test SDRAM? I know about walking 0's or walking 1's algorithm but I did not find out what algorithm it uses to identify a module where a possible problem is( if there are more modules e.g. DIMM with more SDRAM chips(module)).
How I know that a particular address belongs to a particular module?
Does anyone know that ?
Thanks
Unfortunately it is very complicated - I once tried to make a ram interface (using an FPGA), I never want to do that again!
It's hard to think of a way you might be able work out easily which module is at which address. Do you have any test gear (oscilloscope, logic probe) you can connect up to the boards while they are running? If you do, try connecting it to CS on one of the modules and see if there is more activity on the CS line when your memory test is running at certain parts of the address space. Or by connecting to one of the data lines and using some specific data sequences (say 0xffff0000 0xffff0000 oxffff0000 .... and 0xffffffff 0x00000000 0xffffffff 0x00000000) you might be able to work out if data is interleaved.
If you don't have test gear you might need to think of a way to cause a temporary fault in a module so your memory test can detect it. I can't think of a good reliable way to do this. It would help if you had a module you knew to be faulty, then you could just do a memory test, move the bad module around, and observe how the faulty address changed.
The CPU can complicate things further if it has cache and/or an MMU. With cache, writes and reads won't happen immediately but will be queued up and blocks of memory will be written and read in one go. With an MMU any memory address can be remapped anywhere else so there's no knowing what chip an address will end up on.
Thank you for the reply.
Thant is a good idea to check CS bit. I have a logic analyzer too but I was told it is not fast enough to check data /address bus but for CS it could be OK, I think.
But still I do not understand nterleaving.Do you mean that some time only some modules are used and the other time other modules?
Yes, the task can be quite complicated( maybe even difficult) but if operating system ( running in that embeded device) can know where and how to write and read, it must be workable.
Thanks again for help and ideas.
"Interleaving" is just the proper term for your second example. So when you wrote:
1st address in module 1
2nd address in module 2
3rd address in module 3
4th address in module 4
5th address in module 1
6th address in module 2
7th address in module 3
8th address in module 4
..
..
the last but one address in module 3
the last address in module 4
The correct term for this is "interleaved memory".
For your first example:
1st address in module 1
2nd address in module 1
3rd address in module 1
4th address in module 1
5th address in module 1
6th address in module 1
7th address in module 1
8th address in module 1
...
...
the last but one address in module 4
the last address in module 4
that is called "non-interleaved memory"
What I meant in my first post was that there are other kinds of interleaved memory. The most common way is this:
1st address in module 1
2nd address in module 2
3rd address in module 1
4th address in module 2
5th address in module 1
6th address in module 2
7th address in module 1
8th address in module 2
...
...
the last but one address in module 3
the last address in module 4
Thank you for the reply.I made few more tests.But before I describe them a word or two how memory modules are connected.
There are 4 SDRAM modules. Let's mark them as U2,U3,U4,U5. The modules U2 and U4 have its own clock( from CPU) and U3 and U5 have also own clock( but different from those used for U2 and U4).
To check how memory is connected I removed/desolder connection from a particular module and used my program for the memory testing( I used walking 1's algorithm).E.g. I removed pin 2 of U2 SDRAM and ran memory testing program.
The program started from 0 address and went up.
So I removed pin 2 of U2 SDRAM and ran test.then I noticed that CPU writes to this module( U2 module) if there are addresses such as 12,28,44,60 ... that is a multiple of 16
Then I connect/solder again the previously removed pin 2 of U2 SDRAM and now removed pin 2 of U3 SDRAM module. Then I found out the CPU wanted to write when the addresses were 24,40,56,72 and so on.
By comparing the differences I found out that there is a 4-address-gap. So It seemed( perfectly) interleaving like
1st address in module 1
2nd address in module 2
3rd address in module 3
4th address in module 4
5th address in module 1
6th address in module 2
7th address in module 3
8th address in module 4
..
..
the last but one address in module 3
the last address in module 4
but I went on to solder back pin 2 of module U3 and now removed pin 2 of U4 SDRAM module.
As you can see above between addreses ( 12,28, 44, 60 which belongs to U2 and addresses 24,40,56,72 ... that belongs to U3 is a room for 2 more addresses( modules). ( Each address of a module has a 4-address-gap).So I guessesed that addreses 16(12+4) should belong to U4 and 20(12+8) to U5 .Also for example 28+4=32 belongs to U4 and 28+8=36 to U5.
But I could not found any difference when removed pin 2 of U4 SDRAM module.It seemed as if nothing was removed.
So I tried to increased addresses but I did not find difference either.
Does anyone have any further idea how module U4 and U5 are used ?Or how should I test it?
Thank you
Can you post the code you use for the memory testing? Is it running on the same computer, or is it on another machine and using JTAG?
If it was running on the same computer and the cpu has an MMU, it might be doing address translation. If you allocate memory on Linux it doesn't map it to physical memory until you write to it. If you allocate a big piece of memory and just write to the end of it, LInux might remap that piece to the beginning of physical memory. To get around this, write 0 to every address in your memory allocation before you do anything else.
Some embedded linux systems have a command called devmem or devmem2 which bypasses address translation and writes directly to physical memory locations. If you use it you have to be very very careful because if you accidentally write to an address that Linux is using it will crash. JTAG should also bypass the address translation I think (but I've never used it so I don't know for sure)
Thank you for your reply.
I use JTAG, so there should not be any address translation.Besides I use DMA( direct memory access) with JTAG.
Yes what was true about U4 module, the same was with U5 module.
Do you have any idea what I should try now?
And why do you think U2 and U4 have its own clocks and U3 and U5 also ( but different from U2&U4)?
Thanks
Try every address in the 32-bit address space. U4 and U5 must be in there somewhere.
Do you know if the ram is single data rate or double data rate? If it is DDR it could happen for example that U2 has addresses 4 and 12, but address 4 gets written very very quickly before address 12 and you didn't see it (it would be there for less than half a clock).
The clocks to U3 and U5 could be the same as U2 and U4 but buffered (it's not good to have one clock signal driving too many things without buffers). Or it could be 90 degrees out of phase, so that the CPU can write to U3 then write to U2 a quarter of a clock later (and if it is DDR, it could write to U3 again after half a clock then U2 after 3/4 of clock)
Try every address in the 32-bit address space. U4 and U5 must be in there somewhere.
Do you mean I should use 232 addresses?
Do you know if the ram is single data rate or double data rate?
The datasehhet says:
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
And yes,it is DDR SDRAM
If it is DDR it could happen for example that U2 has addresses 4 and 12, but address 4 gets written very very quickly before address 12 and you didn't see it (it would be there for less than half a clock).
Do you mean that it writes to different modules for the same address?
The clocks to U3 and U5 could be the same as U2 and U4 but buffered (it's not good to have one clock signal driving too many things without buffers). Or it could be 90 degrees out of phase, so that the CPU can write to U3 then write to U2 a quarter of a clock later (and if it is DDR, it could write to U3 again after half a clock then U2 after 3/4 of clock)
The CPU datasheet marks clocks the same. Only as DDR DRAM clocks - both for U2/U4 and U3/U5. But if one clock does not work( e.g by disconnecting clock from the memory - either from U2/U4 or U3/U5,) the device itself does not start at all. ( CPU does not execute any further program from BIOS).Is that because it is interleaved mode for the SDRAM used?
Thank you for help
Try every address in the 32-bit address space. U4 and U5 must be in there somewhere.
Do you mean I should use 232 addresses?
Yes, try every address there is. There must be some addresses where U4 and U5 are.
Also, try to find the highest addresses for U2 and U3. Then you might find addresses for U4 and U5 after that.
If it is DDR it could happen for example that U2 has addresses 4 and 12, but address 4 gets written very very quickly before address 12 and you didn't see it (it would be there for less than half a clock).
Do you mean that it writes to different modules for the same address?
No, it writes to the same module for two different addresses, but it writes the first one so quickly that you won't see it unless you have a very fast logic analyser. That might be why you can't find address 16.