12-bit DAC output

Guys,
Got my first code going with a DAC.
Is there anything more I can do to speed this up a little?
Driving 4 of these with 2 outputs each.
Not going for audio quality here, will be remoting the voltage level of some pots.

MCP4922, dual DAC SPI.pdf (3.62 MB)

Do you mean, faster than 7 Hz? lol

I made up your circuit because I happened to have that chip lying around. :)

I typed in your code (can't include from an image) and tested.

The scope shows a frequency of around 7.6 Hz.

That would be confirmed by the screenshot of the logic analyzer. It takes 10.5 uS to send out one 16-bit value. That sounds about right as I reckon a single SPI byte to be about 3 uS, plus turning SS on and off. So that sounds OK, you can't do much better than that. Then another 5.5 uS for adding, and the loop etc. Total of 16 uS.

Now you are doing 4096 values up and 4096 values down to get one cycle. So 8192 * 16 uS = 131072 uS.

So your frequency is going to be 1 / 0.131072 which is 7.629 Hz, which exactly agrees with the observed frequency.

To speed it up? You could add more each time (eg. add 2 on the way up, subtract 2 on the way down).

But for remoting pots, well responding within 1/7th of a second is OK isn't it? But as I said, if you want faster, just add more each time. Of course, if you just want to jump from a setting of 500 to a setting of 1000 (with no intermediate steps) then that will take you 16 uS.

Clock High Time tHI 15 — — ns Note 1 Clock Low Time tLO 15 — — ns Note 1

30 ns --> 3 1/3 MHz maximum data rate (assuming I'm interpreting the datasheet correctl)

Even though it will exceed the data rate of the DAC (I think) add this to the bottom of setup...

SPI.setClockDivider( SPI_CLOCK_DIV2 );

Thanks guys, will add the SPI divisor & try again.

2nd question:
In void loop, I get this compile error:
‘DAC_B_mode’ was not declared in this scope
How do I fix it?

Never mind, some comment line was screwing up the other part. Got it fixed.

Get rid of the backslash on the previous line. That joins them together.

[quote author=Coding Badly link=topic=100667.msg754915#msg754915 date=1334028746]

Clock High Time tHI 15 — — ns Note 1 Clock Low Time tLO 15 — — ns Note 1

30 ns --> 3 1/3 MHz maximum data rate (assuming I'm interpreting the datasheet correctl)

Even though it will exceed the data rate of the DAC (I think) add this to the bottom of setup...

SPI.setClockDivider( SPI_CLOCK_DIV2 );

[/quote]

There's not much point. Even if you double the speed you only get 14 Hz. And the limiting factors now are the speed with which you can go through the loop.

Thanks, Got the code fixed in between comments. Gonna download now & see how it goes.

Woo hoo! Got 12-bit DAC outputs to follow pot inputs via 12-bit ADC inputs over an RS232 link at 115200!

Now to add in some more IO, read some switches and send those along too.

[quote author=Nick Gammon link=topic=100667.msg754921#msg754921 date=1334029802]There's not much point. Even if you double the speed you only get 14 Hz. And the limiting factors now are the speed with which you can go through the loop.[/quote]

True. But I was curious to know how the DAC would behave. ]:D

Testing that, the DAC seemed OK.

But you can see the savings are minor, because the bulk of the time is in the loop, not the transfer itself.

This has shaved 2 uS off each transfer, and the frequency is now 8.66 Hz.

Testing that, the DAC seemed OK.

Huh. So did I misread that datasheet?

Which part? Are you surprised it worked? The datasheet says 16 MHz clock support (in the bragging part at the start). With your change we are using a 8 MHz clock. So it's within spec.

The bit I included in my post.

Are you surprised it worked?

I am.

Give me a minute to find the page / figure…

5.0 SERIAL INTERFACE
5.1 Overview
Refer to Figure 1-1 and SPI Timing Specifications Table for detailed input and output timing specifications for both Mode 0,0 and Mode 1,1 operation.

Off to Figure 1-1… The timing diagram includes the SCK signal with the high level labeled tHI and the low level labeled tLO. In the table above the diagram tHI and tLO both have a minimum value of 15 ns. 1 / ((15+15) * 10e-9) = 3,333,333 MHz.

I realize chip vendors publish guaranteed numbers but, assuming I’m reading the datasheet correctly, 8 MHz is more than twice the maximum bitrate.

Figure 1-1 in the datasheet: Clock frequency: 20 MHz max.

And this is on the first page...

SPI Interface with 20 MHz Clock Support

Agreed, it doesn’t make any sense.

Oh, wait. I was multiplying by 8. That works out.

A 20 Mhz clock would be 50 nS period. So 15 + 15 = 30 fits within 50 nS.

[quote author=Coding Badly link=topic=100667.msg754955#msg754955 date=1334033294] I realize chip vendors publish guaranteed numbers but, assuming I'm reading the datasheet correctly, 8 MHz is more than twice the maximum bitrate. [/quote] 15ns * 2 would put max frequency at 33.3 Mhz. For a 20Mhz chip, min t-low and t-high at 15ns seems a reasonable specification to allow for rise and fall times. 8 Mhz should be just fine.

Argh! 1e-9 not 10e-9! Never mind.