It actually depends on the type of interrupt. Here's how the spec sheet explains it:
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user soft-
ware can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current
interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writ-
ing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding
interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the
flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit
is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is
set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not nec-
essarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will
not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction
before any pending interrupt is served.
I don't know if the ethernet interrupts are level triggered or edge triggered. I expect they are edge triggered, and it should queue them up.
Timer interrupts are edge triggered and will queue up just fine. The only problem would be if somebody took so much time in the ISR that two interrupts hit before the first one was handled.
The other problem would be if more than one interrupt were to be multiplexed onto one interrupt pin. For example, Pin Change interrupts. If you happened to be handling a higher priority interrupt and got two pin change interrupts that were multiplexed to the same PCINT, the PCINT would be queued up, but the ISR would only be called once and you would have to figure out in the ISR that two pins had changed.