Grumpy_Mike:
Not quite. A digital time base is a chain of counters that produce the digital signals you need for the display.
You need several divide by N counter chains. Basically you use logic gates to detect that the counter has the required value on the outputs ( you only need look at the logic ones ) and then use the output to reset the counter back to zero. Here is an example:-
www.techlib.com/files/161divdr.pdf
Ah I see. But since I need a pixel clock of ~25mhz, wouldn't that require my master clock (the one sending the actual pulses), no matter what my devide-by-N is (N>1 ofc) to be at least N times faster than
~25mhz ? Maybe that RAM burst mode helps-I am not really that much into that yet. My idea was just very simple to have a counter, activate all "screen"-addresses of the SRAM, then the counter resets every frame sync.
But I presume i can get a 25mhz clock and then divide-by-N to get the vertical/horizontal syncs, right?
Grumpy_Mike:
No the stability is the same as the source what you get is the frequency you want locked to a master clock. In this way the frame sync pulse is locked to the line sync pulse.
Right - I think that was what i meant 
Grumpy_Mike:
That was because XVGA used different frequencies to the normal VGA. At best they were never going to lock.
Yearh at best.. thats an advice my old monitor could have used.. sigh.. that was as fine 14" CRT that was..
Grumpy_Mike:
What was done normally was to have the RAM connected to a parallel input / serial output shift register. The shift register was clocked by the master clock ( fastest ) and then the Arduino would only have to change the address at one eighth of this rate.
However, the whole point about a digital time base is that it provides the logic signals to address the memory. You then only need to switch that memory address to the Arduino when the Arduino needs to change the memory contents. This produces a visual glitch on the screen so it was common to do this change over only during frame sync pulses where it would not be seen.
Actually, my idea, because this is kinda a real problem I think, with the syncing of frames, was to have a double buffer, in SRAM. That is, one ram is Write-to-ram, one ram is Read-From-Ram. Clock pulses activates one piece of RAM sending data to VGA, while the arduino has ability to write to the other block of RAM. When a screen is done being written by the arduino the arduino waits for frame-sync is present (60 times a second, should happend more often than a complete screen write on the arduino), the READ and WRITE ram is swapped, and both processes can continue. This limits the framerate of the arduino. But to be honest, I dont see that as a problem - right now 
Grumpy_Mike:
You could also look at a chip known as dual ported RAM. This allows two sets of address lines to access the RAM at the same time, one from the time base reading things out and the other from the controlling micro, in this case the Arduino.
Yes I have, they are quite expensive (and less fun to work with, since.. they work). I decided to go the doublebuffer way instead. Also, I looked into RAMDACs for that extra layer of fine all-inclusive experience, but decided that I wanted to go another way. At the moment I am working towards applying palette with a 8bit addressable, 16 bit word SRAM block, in goes the color from SRAM, out goes the 16 bit RGB instead. However, I am yet to finde one of these >8bit adress, 16bit word, SRAM, where i can access it 