64K address space best approach?

I'm trying to interface several devices that use 16 address lines and I've yet to come up with anything that seems elegant. So, I was wondering if a standard or simple setup exists. Right now I'm working on using four separate 4bit programmable counters with a demultiplexer on their load lines. It should work and make sequential reads/writes pretty easy, but 5 chips seems excessive. Are 16bit shiftregisters readily available?

Thanks.

At least they exist: 74XX674 and 74XX675

So they do. Though I can't find any place that stocks either. An individual on ebay has some for $13 including shipping. I'd rather use a micro with more GPIOs than a $13 shift register.

Do you need to use counters? Is that because you want the speed of just pulsing once per read/write?

Do the devices have chip select pins? With 2 shift regs and one Arduino pin per device (if they have CS) you're done.

No, I don't need to use counters, but I figured they would work as well as latches and increment nicely. Speed is not a factor. I'm working on a Gameboy cartridge reader and a simple EPROM emulator. They are separate projects and don't share any connection. I just realized I have two 74ls164 chips. I don't really like using multiple shift registers, it's worth saving the GPIOS and chips. I guess that's what I'll do. Are their any craft ways to set them up? They can share the serial line but each needs it's own clock line right? Or could you tie bit 8 of one to serial in on the other and share a clock?

Shift registers can normally be cascaded so that any length of thing can be implemented with the same number of Arduino pins. Shared clock, shared latch, input of one connected to last output of the previous oneā€¦

I don't know much about the internals of shift registers, but sounds like it would be a race condition. If you clock the registers at the same time does the cascaded register read before, after or during the first register's shift? Anyway, if it works, it works.

I'll go try cascading the registers.

Thanks for the input everyone.

You didn't say what the "devices" were but as this is an EPROM emulator I assume 64k SRAMS?

In that case they have CS inputs so you can control them individaually,

set address with the SRs select the active SRAM read/write pin = 0 read/write read/write pin = 1

Normally though with an emulator (unless you're using dual-port RAMs) you need to mux the data and address lines as well. Is that the case here?

but sounds like it would be a race condition

No race condition, on clock all SRs shift in whatever is preseneted on their input pin and this has been stable since the last clock. So they all sample stable data at exactly the same time.

I'm doing it barebones with a single 6264 64K sram. But yeah, if I wanted more storage I could add another chip, put it on the same data and address buss and multiplex with CS.

No race condition, on clock all SRs shift in whatever is preseneted on their input pin and this has been stable since the last clock. So they all sample stable data at exactly the same time.

I don't exactly follow you. Do you mean they sample and then shift? Or do they "know" what was on the input before the clock :P?

I get that they would both sample at the same instant due to them sharing the clock. But, if they shift as they sample the cascaded register(s) could sample the wrong bit.

do they "know" what was on the input before the clock

Yep, the data for all flip-flops in the chain (8 per SR) has been stable since the previous clock pulse, so when the next clock comes along they "know" what the data is and simply shift it to their output pin. Because they all do it at the same time the data N is already sampled a few nS before the data N+1 arrives.

Note that while doing this the 164s outputs will ripple the data through, as long as the RAMs CS pin is high this will be OK though.

Well I feel like a bit of an ass. So they read on the falling edge and shift of the rising? If not, what causes the delay?

Yes, I know that shift registers shift. And I know what CS does. I'm not that dense. ;D

So they read on the falling edge and shift of the rising? If not, what causes the delay?

A picture is worth a thousand word. Just select a shift register chip candidate and search and download it's data sheet. There will be timing diagrams showing all the timing details along with specifications for set-up times, etc.

Lefty

Ok. The datasheet doesn't explicitly say how the delay works but it does mention a propagation delay of 19ns. So I guess it reads, waits and shifts. None of this really matters anyway.

Thanks for sharing. Now I know I can build a 16 bit register.