74595 detail question

I’m using a 74hc595 as part of adding a high speed spi input to an old-school micro that only has parallel input. My MISO is the 74595 serial input and the parallel outputs are gated onto the data bus with the /OE input.

looking at the 74595 data sheet here http://www.nxp.com/documents/data_sheet/74HC_HCT595.pdf the logic diagram shows that /OE is separate from the shifting and storage register functions but the transition diagram shows the shift register clocking into the storage register only when output is enabled. I’m not sure whether this is just a consequence of how the part is usually used or an actual restriction. Has anybody used the 595 in a similar way?

The logic and transition diagrams are attached.

74595-logic.jpg

MOSI (pin 11 on Uno) would be routed to 595 serial input. You can transfer the shift registers to the output registers with oe* high (outputs tri-stated) with the store pin edge. I have used in a very similar situation. I used 595's to interface to parallel SRAM.

ok great - thanks. I've also ordered a 74HC4094 which has a level rather than edge sensitive output register load so i can just leave it open.

OE/ turns on the output drivers, letting several parts be connected on parallel and letting one part at a time drive the resulting "bus". OE/ has no impact on shifting data into the first stage, or into the output stage. The chart only shows that the outputs will be valid (and not tri-stated, or Hi Z) when OE/ is low.