I'm just wondering if this is correct way of connecting 74HC595 with decoupling capacitors. If not - please correct me.
Supply and ground tracks should be a lot wider. They should be routed directly to the capacitors, and from them to the 74HC595 pins. Route them first.
Just use round pads for the IC chips, so they don't come close to the diagonal copper traces.
I would run the V+ and V- lines straight inside the chip's outline, so they're not weaving in and out.
Can you use Vias? I think it would make for a cleaner and simpler layout.
[quote author=Leon Heller link=topic=138652.msg1041476#msg1041476 date=1356196701]
Supply and ground tracks should be a lot wider. [/quote]
How much wider? My current setting is 0.016 (inches?) in EAGLE.
Hm, isn't that what I've done?
vasquo:
Just use round pads for the IC chips, so they don't come close to the diagonal copper traces. I would run the V+ and V- lines straight inside the chip's outline, so they're not weaving in and out.
I'm not sure I understand what you mean. I basically just started doing stuff in EAGLE couple of days ago.
vasquo:
Can you use Vias?
Yep.
Click DRC (Design Rule Check), click the Shapes tab
Under Pads section, "Top" and "Bottom" pull down menu, change from "As in library" to "Round"
Hm, isn't that what I've done?
If you look at your V+ line, it's weaving in and out... just run it straight through your (2) chips. Then branch off to your caps and pins. You may need to reroute the other traces or use vias if they need to "cross over"
vasquo:
Click DRC (Design Rule Check), click the Shapes tabUnder Pads section, "Top" and "Bottom" pull down menu, change from "As in library" to "Round"
Okay, did that.
vasquo:
If you look at your V+ line, it's weaving in and out... just run it straight through your (2) chips. Then branch off to your caps and pins. You may need to reroute the other traces or use vias if they need to "cross over"
Is this better?
No.
EDIT1: I meant like this, see attach.
EDIT2: If I were you, I wouldn't even bother routing the GND... just fill up the top/bottom with a ground fill and let Eagle take care of connecting the GND pins.
vasquo:
No.EDIT1: I meant like this, see attach.
Thanks for help.
vasquo:
EDIT2: If I were you, I wouldn't even bother routing the GND... just fill up the top/bottom with a ground fill and let Eagle take care of connecting the GND pins.
Well this is 2-layer board (there are lots of other chips on the board actually), so it seems like I can't just fill one of those layers with GND. Or is there some other method?
so it seems like I can't just fill one of those layers with GND.
Why not? I do it all the time. Eagle will add the necessary clearances to your other non-GND connections and your ground fill will "wrap around" those connections. You can control how close/far apart the ground plane should come to these paths in the DRC.
vasquo:
so it seems like I can't just fill one of those layers with GND.
Why not? I do it all the time. Eagle will add the necessary clearances to your other non-GND connections and your ground fill will "wrap around" those connections. You can control how close/far apart the ground plane should come to these paths in the DRC.
Awesome, thanks again. One more question - "You can control how close/far apart the ground plane should come to these paths in the DRC. " - > where is that option in DRC?
Under Clearance and Distance tabs.
Put your cursor in each input field and you'll see a representative diagram/figure of what you're adjusting.
vasquo:
Under Clearance and Distance tabs.Put your cursor in each input field and you'll see a representative diagram/figure of what you're adjusting.
Aha. How much clearance is preferable in most cases?
10 mil is sufficient. You have access to a fine tip soldering iron and thin solder?
Ground planes are done by selecting the polygon tool, drawing the outline, then use the name tool to name it "GND" and hit ratsnest - bingo!
For a complex 2 layer board you'll need ground planes both sides and to add various GND vias to prevent "polygons have fallen apart"
messages. You add a ground via by selecting the via tool, plonk it down, then rename it "GND". Thereafter use the copy tool to
duplicate ground vias as you wish to keep both ground planes connected. Its fun (honest!).
Power wiring should be 0.04 or 0.05 if possible, and add decoupling caps near the supply pins of the chips with as short a trace as
possible - short fat traces over a ground-plane = low inductance path to decouping cap = good practice.
Rule of thumb is play around with component placement till happy, then route the supply wiring and add ground planes. Then try
the autorouter for the rest (then spend ages improving on it). Save frequently.
If you want to start dabbling in surface mount then try using 1206 or 1210 sized 0.1uF decoupling ceramics - you'll save some board
area compared to through-hole caps and 1206 isn't horribly tiny.
If you look closely at the application and parts used there is nothing wrong with the original layout. for several reasons. I do hope I don't make the PCB experts unhappy BUT there isn't enough current capacity per package to warrant bigger or more Power and ground traces.
True there is a 20 mA/Pin limitation which would lead Obviously to a 160 mA capacity/package - 320 mA total capacity But that 20 mA is per a single pin only. The Max Package Current through Vcc Or Ground is 35 mA for a 70 - 80 mA total load current and the speed of the package isn't great enough to cause any real issues.
The last cause of RFI/EMI is fast switching and the resistor/output transistor driver circuit on the outputs should clear up that last source of noise.
One of the best means of lowering noise generated on the power supply lines is to slightly 'isolate or decouple the gate of the mosfet from it's driver and more than anything else it lowers the noise by lowering the 'short circuit' current drawn by the gate capacitor of the mosfet on turn on and thus reducing or eliminating that current spike on the power supply. It's a great help with bread boarded S/R's but not in any way to fix low or no appropriate bypassing. I took the liberty of uploading a 74HCT595 data sheet for reference.
Bob
74HCT595.pdf (136 KB)
You're right.
It will work as is, in the original layout.
BUT it looks like OP will have the boards manufactured (being double-sided)... and since there's no cost penalty in making your boards look pretty, better designed and more robust... why not?
As for the wider traces, it's not just about current. I've found wider traces also have stronger adhesion to the laminate vs. thinner traces, and if you're working the board, debugging, soldering/desoldering, the wider traces helps... Again, there is no cost penalty, there is more than enough real estate on the board, so... why not?
He'll pay the same amount to the PCB house, whether he submits his original design or a better, improved board layout.
My 2 cents.
Docedison:
If you look closely at the application and parts used there is nothing wrong with the original layout. for several reasons. I do hope I don't make the PCB experts unhappy BUT there isn't enough current capacity per package to warrant bigger or more Power and ground traces.
Wide supply and ground traces are for low impedance, not just low resistance (ie low inductance in the 100MHz range).
When you switch significant current (such as 20mA to an LED) at logic speeds, the rate of change of current is
simply HUGE - 74HC family transitions in 5ns or so, so 20mA is switched in 5ns, equivalent to 4 MA/s - and even 100nH
of stray inductance in each power/ground lead will cause 0.4V dip in the supply at the chip. Have 8 outputs each switch 20mA and that
becomes 32 MA/s - ie a 3.2V supply-dip - result is almost guaranteed circuit malfunction!
Put another way the resistance of the PCB trace is a few milliohms, the impedance at 100MHz is ~ 10 ohms/cm, inductive
reactance totally dominates! But traces do have to be wide enough not to overheat - 8 x 20mA is 160mA and
that's not too much for standard logic traces, but you will lose some voltage over a long thin trace to IR losses...
100nH is the sort of stray inductance from 7.5cm of 0.25mm wide PCB trace. Most benefits come from shortening traces but
wider traces lower inductance too. (1cm of 1.5mm trace is only 6nH, but 1cm of 0.25mm trace would be 19nH, three times as much).
[ see formulae in fig 12.18 of http://www.analog.com/library/analogdialogue/archives/43-09/EDch%2012%20pc%20issues.pdf ]
Actually you can happily run the power rails as 0.25mm traces from the power connector to the decoupling cap, but widen
between the decoupling cap and the IC pin - this is where inductance matters most.
Is 40mils okay then for both power to caps and from caps to IC? What about other traces - 12mils is okay?
.04 is okay.
.012 - if you don't necessarily have to use it (for example, you're using fine pitch SMD), I would suggest for your Through-Hole components, I'd stick with .04 too, or .032, or .024.
I think you have room on the board, just make everything .04.