A clear and simple flow

Hi all.
I want to make my own FPGA projects.

1- I develop it into Quartus 18.1 Lite using the MKRVIDOR4000_template found on GitHub,
then compile and generate the .ttf file
As first step a simple 7-bit counter using as output the MKA_A pins, eliminating all other logic
from the MKRVIDOR4000_top.v file
--> done (Modelsim fails to find dffas module in its libraries, but this is an Intel open case)

2- As sketch I use "template_bare", why not?
How to proceed?
--> it seems I need to compile the Quartus output in a "Arduino library" using the
assemble_library.sh provided with the VidorBitstream-release

It is a bash shell script so I need a Linux shell on my Win10 PC, right?

When I have this compiled library, what next?

Thanks for the help
Fabio

You can run these shell scripts in NIOS II Command Shell. This uses cygwin linux shell so you can run all provided scripts from here.
You just need to add script folder to path that you can run these under current project folder.

OK, now I have Cygwin.

The folder structure is as in attachement, project folder is MKRVIDOR4000_prova.
In which folder to go in order to run the script?
What should be the result (what folder should be created, what files, what to do
next) ?

Sorry to ask for that but I cannot find any instructions.
Thanks
Fabio

structure1.jpg

structure2.jpg

structure3.jpg

if you configure your arduino vidor 4000 as USBBLASTER SAM emulator
you can generate a fpga bistream with altera quartus ( .sof file ) and upload directly from altera quartus

( and generate arduino code with ttf only at the end of fpga project development)

so

this opens another branch to my main attempt to write a FPGA+Arduino custom project.

When the main flow will work I'll try with USBBlaster, thanks.

Hi famo,

To make things a bit more (less?) confusing, I actually found that Philippe's guide is slightly less cumbersome to follow, as it only requires one extra java program (apart from the arduino ide). Google translate actually does a good job in translating his step-by-step tutorial:
https://translate.google.com/translate?sl=auto&tl=en&u=https%3A%2F%2Fsystemes-embarques.fr%2Fwp%2Ftelechargement%2F

While I was writing this post I’ve received the reply from ergoen.
Thank-you, I’ll go to see your link, anyway my post is below.


Well, this is what I learned so far:

1- the VidorBitstream-release comes with a BareMinimum stuff:
VidorBitstream-release/projects//software/arduino/examples/BareMinimum/BareMinimum.ino
. …/src/

If I try to compile BareMinimum.ino the only way to success is to copy the src folder
in the same BareMinimum.ino folder and to change the #include path
→ why? If this is really the only way to compile, why to distribute a wrong file structure?

So I have to copy src as /examples/BareMinimum/libraries folder and change the #include path
to “libraries/xVidorTemplateBare.h”

The Quartus project seems must be placed here:
VidorBitstream-release/projects//projects/

If I try to load in Quartus the BareMinimum project the CycloneV is the selected family,
no constraint files linked and so on, so I’ve rescued my previous simple project from
MKRVIDOR4000_template.

2- I can see the src folder contains the .ttf file, very likely copied (to be done by hand?)
from the Quartus project folder.

3- the VidorBitstream-release has a TOOLS/scripts folder with the assemble_library.sh that should
be the script to be executed in order to have a not well defined “distribution library”.

Where to run the scripts? After several attempts, very likely in project/.

If I do that a VidorBitstream-release/distrib folder is created, here the Cygwin log translated
to english:

cp: impossible to execute stat of ‘./projects/MKRVIDOR4000_prova/build/output_files/app.ttf’: No such file or directory
cp: impossible to execute stat of ‘./projects/MKRVIDOR4000_prova/build/output_files/signature.h’: No such file or directory

My Quartus project doesn’t contain the build folder. I can copy manually the app.ttf file but
I cannot have a new signature.h file, I keep the existing one in the VidorBitstream-release.
—> If it is wrong, where to find/how to generate it?

So, what is the distrib folder content?

/examples/BareMinimum/BareMinimum.ino
…/BareMinimum/libraries/
…/src/
All seems to be a simple copy of the working folders.

4- Well, what next? I suppose I have to load all into the board.

I open the BareMinimum.ino in the distrib folder, compile and load it into Vidor4000.
There are no errors, but the simple counter bits in FPGA I’ve done are not visible on the A[6:0]
board pins.
Very funny: I cannot simulate the Quartus compiled circuit because Modelsim doesn’t find
dffsa unit … still no answer from Intel.

Note that if I modify the .ino in the distrib folder there are some permission errors, so the
distrib seems for “as is/read” use only.

OK, if I don’t see the counter pins could be my error, but why I cannot find somewhere
a simple production flow from a Quartus/Verilog empty template to the final board programming?
I don’t need now IPs or Nios o whatever, I need simply to write my own Verilog code, produce
the right programming files and to program the board.

In the “Arduino stile” it should be easy and perfectly documented, isn’t it?
I’m able to do the Quartus project but following steps are not explained.

I’m still waiting for someone who has already done what I’m trying to do, so he can
explain the right flow.

Thanks again
Fabio

ergoen:
Hi famo,

To make things a bit more (less?) confusing, I actually found that Philippe's guide is slightly less cumbersome to follow, as it only requires one extra java program (apart from the arduino ide). Google translate actually does a good job in translating his step-by-step tutorial:
Google Translate

Here some results following your link.

The FPGABlinkLED_Sketch/_FPGA is supposed to be a 26-bit counter usign an
"80-MHz FPGA internal oscillator" instantiated in the Verilog file as cyclone10lp_oscillator.
The MSbit is routed to the board MKR_D[6] pin that should be the connector pin marked "6".

If I load the FPGABlinkLED_Sketch as it comes from the above web site, the load time on
Vidor4000 is 4.670 seconds.
After the automatic reboot the red led is steady ON (checked with an oscilloscope) and
the aboce pin "6" is steady = 0.

If I recompile the Quartus project, change the app.h with a new app.h (Quartus output.ttf),
the load time is 11.878 seconds but the result is the same.

In both cases none of the 14+14 connectors pins toggle, the red led is steady ON.

Well, another black hole is in front of me:

  • is the FPGA internal 80 MHz clock running? I could route it to a board connector pin and see ...
  • is the output.ttf --> app.h copy the right thing? No idea.
  • is there someone in the world able to see this "tutorial" working? I'm do not!
  • is the so called "tutorial" buggy? (if yes, no hope for me)

Loading the FPGABlinkLED_Sketch I can verify with an oscilloscope that the red led is steady ON,
not pulsed

- is the FPGA internal 80 MHz clock running? I could route it to a board connector pin and see ...

Done, nothing is "running", but looking into .ino I note this:

// Disable all JTAG Pins (usefull for USB BLASTER connection)
pinMode(TDO, INPUT);
pinMode(TMS, INPUT);
pinMode(TDI, INPUT);
pinMode(TCK, INPUT);

Strange, there is an #include "jtag.h" but the pins are later disabled?

Anyway, is the bootloader that programs the FPGA or the JTAG/USB Blaster software is
required in each Arduino project to have a FPGA programming at boot time?
Is the GitHub - vidor-libraries/USBBlaster mandatory?

Why nobody from Arduino staff gives some reply?

Hi famo,

my tutorial should work without problem. Many users have succeeded.

I disable JTAG pins because (in my case) there are only used in the Init phase (to tell the FPGA to load a user configuration).

The pin which should toggle is the pin marked “6” on the MKR connector (the board LED red is not driven by the FPGA)

To test the internal oscillator clock, you can output it on another connector pin :
try to add "assign bMKR_D[7] = wOSC_CLK; " in top level file.

Perhaps FPGA user configuration is not load : if you have a HDMI screen, try to connect it (Arduino logo should disappear when my configuration is loaded).
Also if you have a screen connected , you can try my sketch which used DVI out.

Hi famo,

Just running Philippe’s FPGABlinkLED_Sketch through the Arduino IDE (with the pre-supplied app.h) produces the behaviour on my Vidor as shown in the attached video. (My LED has a built-in resistor)

I did encounter similar problems to what you are describing before (where nothing really happened irrespective of what I was trying to load). For me, this was a firmware issue, I had to restore the bootloader according to the other thread on this forum and then update to the latest bootloader through the Arduino IDE (File->Examples->(Examples for Arduino MKR Vidor 4000)->SAMD_BootloaderUpdater

blinking.mpg (1020 KB)

I think first vidors had very bad bootloader and I recommend to do bootloader update for it.
I also had uploading problems before update. About 1/25 times it was working.

I more like to use USB Blaster clone. Recommend to take copy of vidor_bare project and start with that. In that project it also includes pinout file from constraits forder. Without that file it's really mess when synthesis randonly place pins.

ergoen:
Hi famo,

Just running Philippe's FPGABlinkLED_Sketch through the Arduino IDE (with the pre-supplied app.h) produces the behaviour on my Vidor as shown in the attached video. (My LED has a built-in resistor)

I did encounter similar problems to what you are describing before (where nothing really happened irrespective of what I was trying to load). For me, this was a firmware issue, I had to restore the bootloader according to the other thread on this forum and then update to the latest bootloader through the Arduino IDE (File->Examples->(Examples for Arduino MKR Vidor 4000)->SAMD_BootloaderUpdater

I confirm: right now I've reinstalled the bootloader using the VidorFPGARecovery files.
The Philippe's blinking led now works (!) but my own project stops uploading ad 37%.
I remember this 37% has been experienced by someone in the forum, I have to search the thread.

Do you know if VidorFPGARecovery is equivalent to SAMD_BootloaderUpdater?

famo:
I confirm: right now I've reinstalled the bootloader using the VidorFPGARecovery files.
The Philippe's blinking led now works (!) but my own project stops uploading ad 37%.
I remember this 37% has been experienced by someone in the forum, I have to search the thread.

Do you know if VidorFPGARecovery is equivalent to SAMD_BootloaderUpdater?

Very funny: further attempts to load the Philippe's example now hangs all at 62%
(also after power supply reboot)

Hi famo,

I had similar issues, after updating the bootloader with SAMD_BootloaderUpdater, they went away.

Thanks, now the download doesn't hang anymore.

The Philippe's led blink example works each time I upload it but if I recompile it under my Quartus 18.1
replacing the old app.h with the new app.h (app.ttf), I don't see the signal on D6.

Philippe, what is missing?

Just to be sure : Have you bit reverse the stream generated by quartus ?

You have to execute java ReverseByte MKRVIDOR4000.ttf app.h

where :

  • MKRVIDOR4000.ttf is the quartus output file (or anything.ttf)
  • app.h will be the generated file to include in the sketch

Java executable ReverseByte is available here :

https://systemes-embarques.fr/wp/wp-content/uploads/2018/10/ReverseByte_V2.zip

Just to be sure : Have you bit reverse the stream generated by quartus ?

No, I didn't know, only right now I see your site
https://systemes-embarques.fr/wp/archives/mkr-vidor-4000-programmation-du-fpga-partie-1/

before I was directed on
https://translate.google.com/translate?sl=auto&tl=en&u=https%3A%2F%2Fsystemes-embarques.fr%2Fwp%2Ftelechargement%2F

Reversing the byte it works.

Question: is this step mandatory for ANY project or your project has something special?

Tomorrow I'll have to try with my 7-bit counter project from VidorBitstream-release//BareMinimum.

Thanks a lot for your help, at the end I have to write a little user manual for my colleagues.

Sorry, my bad, I thought I had linked the google translate of the guide, not the download page ><.
Reversing is needed for everything you build, also using the “official” scripts, there it is done with a go-program instead of the java one :P.

Well, it seems that if I use the Philippe's project as starting point all works and I'm very satisfied!

Thanks to everyone!

The internal oscillator freq is 66.66 MHz (more or less, measured with a 100 MHz Rigol oscilloscope).
Th external signal iCLK as FPGA input freq is 48 MHz.

Now I'm going to write my experience to be duplicated by colleagues and students.

If I'll have some difficulties I'll post again.

My case at Intel regarding Modelsim simulation is

could be interesting.

Thanks again
Fabio