I've searched the forum. There seems to be several discussions on this eeprom (too bad I didn't see the one where newark has $1.4 24LC512 and I bought from the expensive red box shop again).
Here's a few questions I still have (BTW, My code is working):
The speed was slow. I later found in twi.h the bus frequency was 100KHz and I changed to 400KHz. Here's what I got 3396us for reading 16 bytes if I have a 2.15KOhm pull-up resistor on the SDA. I got 3420um for same 16 bytes if I remove the 2.15KOhm resistor (internal upll-up used). Both are consistent numbers, from multiple experimentation (connect resistor, disconnect, repeat). WHY? Does the I2C bus have some sort of error detection?
Is there any readable materials on the TWI library? The wire library seems to be just a wrapper over the TWI. Now I need to look into how the acknowledge/start/stop bit is sent by atmega328. I can't find the right place to read up on this. Be nice to know when exactly the start and stop bits are sent inside the TWI. When the last byte of write buffer is sent out? When endTransmission is called?
Maybe the real communication only occurs when endTransmission is called?
WHY? Does the I2C bus have some sort of error detection?
No.
It is probably due to the accumulation of time due to the slow rise time when using the internal pull up resistors which are not low enough for correct I2C operation. You should use 4K7 pull ups with 5V on I2C.
Thanks grumpy_Mike.
About the I2C, how do I know if my command was acknowledged? From the data sheet of the EEPROM I'm using, it doesn't acknowledge a command if it's running writing cycle. I'd like to be able to tell after a write operation how soon I can write again by monitoring the acknowledge.
There's way too many layers in the wire and TWI library to make enough sense where to get the acknowledgement.
Here's the original info from the 24LC256 data sheet:
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next Read or Write command. See Figure 7-1 for
flow diagram.
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
It seems the internal pullups are activated in the library in twi.c
void twi_init(void)
{
// initialize state
twi_state = TWI_READY;
#if defined(AVR_ATmega168) || defined(AVR_ATmega8) || defined(AVR_AT
mega328P)
// activate internal pull-ups for twi
// as per note from atmega8 manual pg167
sbi(PORTC, 4);
sbi(PORTC, 5); #else
// activate internal pull-ups for twi
// as per note from atmega128 manual pg204
sbi(PORTD, 0);
sbi(PORTD, 1); #endif
Page 204 says nothing about the internal pullups it leads you to a formula for calculating the minimum and maximum pull up resistor.
The datasheet has the symbol for ohms not kohms. If I blindly ignore the mismatch of V/ma/ns/Cb and assume Kohms then it's 4.8k and 100k. 4.7k is the closes and it's what every website I've looked at recommends. With the mismatch between the atmega sheet and the memory datasheet I'd go with 4.7k. The twi library is turning on the pullups so 4.7k and 10k in parallel will give 4.6k, don't think it should do harm but it would probably be nice if someone made turning those on optional.
V CC-0.4V/3ma
or
1000ns/Cb with Cb being bus capacitance.