ADC not triggering after interrupt

I am trying to use the ADC interrupt to read analog values and am having trouble getting the ADC Start Conversion to start at the end of the interrupt. I have gone though the data sheet several times in the ADC section and am pretty sure I am setting all the registers correctly. When I print out the register values, they are what I expect on the first run. I have tried several different baud rates in the serial monitor so it doesn't seem to be missing messages.

Here is my code:

byte Channel0;

void setup()
{
	Serial.begin(57600);
	
	// ADMUX		= ADC Multiplexer Selection Register
	// REFS0 - 1 	= Reference Voltage Source Choice (AREF, Internal Vref turned off)
	// ADLAR		= ADC Left Adjust Register (shift values to leftmost 8 bits)
	ADMUX |= (1 << ADLAR); 

	// ADSCRA		= ADC Control and Status Register A
	// ADEN 		= ADC Enable
	// ADIE			= ADC Interrupt Enable
	// ADPS2 - PS1 	= ADC Prescalar Bits: 100 = leaving arduino default (128)
	ADCSRA |= (1 << ADIE); // Enable ADC Interrupt
	ADCSRA |= (1 << ADEN); // Enable ADC

	sei();	

	ADCSRA |= (1 << ADSC); // start conversion

}

void loop()
{
 // nothing because we are interrupt driven
}


//fired when signal conversion is done
ISR(ADC_vect)
{
	Serial.println("i");
	Channel0 = ADCH;    // reading the returned value of the high register
	Serial.println(Channel0,BIN);
	delay(1000);
	Serial.println(ADCSRA,BIN);
	ADCSRA |= (1 << ADSC);      // <==== this should start the conversion over again but is not
}

A second question is it seems that the bootloader overrides my settings for the prescaler (ADCSRA bits 2 through 0). For example: I try to set the prescaler to 16 (100) but when I print out the ADCSRA register, I get a prescaler of 128 (111). Am I not setting something correctly or is there some other factor I am not aware of?

I am using an UNO SMD edition with IDE version 1.0.2. I have also tried this with a Diecimila 168 but had the same problem.

Thank you!

Louis

Do not do serial prints inside an ISR.

Do not use delay() inside an ISR.