If I start and ADC conversion, by setting the ADSC bit in ADCSRA, and shortly thereafter (before the conversion is finished) read ADCL and ADCH (in the proper order), will I get
A) The completed result from the previous conversion
or
B) A half-completed result from the current conversion?
This should help. From s26.3 from the atmega 1280 datasheet...
"If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
read, neither register is updated and the result from the conversion is lost. When ADCH is read,
ADC access to the ADCH and ADCL Registers is re-enabled."
That tells me in which order to read ADCL and ADCH, but I still don't know if what I'll read belongs to the current or the previous conversion.
The registers are only valid while ADSC is cleared. Otherwise undefined.
(from what I understand anyways)
I interpret the excerpt to mean that ADCL and ADCH are updated only when the conversion finishes, and only if the result isn't in the middle of being read (ADCL read but ADCH not yet read).
Figure 26-7 of the same datasheet gives a further clue. The ADC timing diagram for free running conversions. The ADC result is shown to persist through the start of the next conversion.
The ADC result is shown to persist through the start of the next conversion.
I was under the impression that is only in the continuous mode.
Let me run a test or 2 
Update: From a quick test it seems to be ok
The reason I wanted to know is that I need to sample a signal at a high and constant rate. From a timer interrupt I started a new conversion and read ADCH/L.
Now, I did'nt want to start the new conversion at the end of the interrupt, because it might take different amounts of time to execute depending on how its if-statements go. And if I start a new conversion at the beginning of the ISR there is the problem of not knowing whether the ADCH/L I read are new or old.
But, there is a better solution! timer1 can be used to auto-trigger an ADC when TCNT1 matches OCR1B with no timer interrupt. Instead, one uses an ADC interrupt. WHen that one starts, ADCH/L are always ready with a completed sample. There is also no risk for interference from timer0's millis-updates: all they can do is slightly delay the time from when the sample is ready until I read it. Using timer interrupts, a timer0-interrupt might delay starting of the next ADC conversion so they are not started at an exact rate.