Adding a new IP Block in Vidor FPGA

Yes, the repository has everything, check the pinned topic: [WORKFLOW RELEASE] Vidor sample projects are opensource!

But note that the project is using some Intel IP that requires licensing (Nios II /f and 16550 UART), so there are two versions of the project - the full, and the "lite" one. The "lite" falls back to free Nios II /e, and disables the UARTs.
I'm not quite sure why the paid uart was used in the first place, you will have to either deal with it (have the license, or replace with other implementation), or tolerate the cores missing.