Always use Pull Up on SPI CS line?

I was reading through the Nick Gammon SPI post here: http://www.gammon.com.au/forum/?id=10896 and saw no mention of putting pull ups on the CS lines.

I was working on a stand alone Atmega328 project and found I had problems with programming the chip via SPI. There were two other slaves on the bus (when programming the processor is a slave too ;)). Once I realized the procesor's pins went into High Z during programming I figured the CS lines for the other slaves were floating. If they floated the wrong way they started chatting up a storm.

I'm working with 3v3. I used 47k pull ups. It seems like it would be easy for the processor to sink what little current gets through. I haven't had any issues, but I also lack the test equipment to see what I'm really doing.

So I'm wondering if one should always get in the habit of putting pull ups on the CS lines. (Pull downs on the few CS lines which work backward.) Any thoughts on this anyone?

I then looked at this post: http://www.gammon.com.au/forum/?id=11518 and saw that the CS line was being pulled low. Here I'm wondering: Why the line isn't being pulled high while the processor is booting? According to the code below, the CS line is active low. I do realize there is no MISO so there is no chance of an chatting by this slave.

digitalWrite (LATCH, LOW);
bbSPI.transfer (c);
digitalWrite (LATCH, HIGH);

(I guess this should be in a different forum but have no clue how to move. Sorry.)

http://www.gammon.com.au/forum/?id=10896 is my I2C post. I think you mean http://www.gammon.com.au/spi

It's a good question and I am trying to remember why.

My best explanation is here: https://www.sparkfun.com/datasheets/IC/SN74HC595.pdf (datasheet for SN74HC595).

The RCLK pin (pin 12) which is connected to SS (slave select) is active on the low-to-high transition. Thus, to not activate it prematurely, we tie it low, and wait for software to bring it high.

[quote author=Nick Gammon link=msg=2102268 date=1424414295] http://www.gammon.com.au/forum/?id=10896 is my I2C post. I think you mean http://www.gammon.com.au/spi [/quote]

Yes, that's the right one. Sorry it's late in my part of the world.

So do you think its a good idea to always externally pull the CS pin into the inactive mode? Unless the part's datasheet specifically says don't like in the shift register part of my question.

[quote author=Nick Gammon link=msg=2102278 date=1424414801] It's a good question and I am trying to remember why.

My best explanation is here: https://www.sparkfun.com/datasheets/IC/SN74HC595.pdf (datasheet for SN74HC595).

The RCLK pin (pin 12) which is connected to SS (slave select) is active on the low-to-high transition. Thus, to not activate it prematurely, we tie it low, and wait for software to bring it high. [/quote]

Yes, I see the pulse in the timing part of the datasheet. That explains it. Always got to remember to pay attention to those things.

BTW, this line of questions comes from having a Maxx DS1391 chatting away on the SPI bus when I was trying to ICSP the Atmega328.

Again, reading the data sheet, I learned that the CS lines were going to be floating during programming. So sometimes the clock chip was quite and other times it was telling me the time.