BTW I see no decoupling capacitor - while this might be OK at DC or for slow applications in a stateless chip like
an AND gate array, you should be instinctively adding 100nF ceramic decoupling caps to each and every logic chip as a matter of course.
Its good practice to connect all the unused inputs from the other gates and connecting to ground or 5V. For
experimentation noone bothers, but if you build a permanent circuit don't forget this. Floating inputs cause
various odd behaviours you probably don't want.